PAST.lvdc
# Copyright: Public domain.
# Filename: PTC-ADAPT-Self-Test-Program.lvdc
# Purpose: This is a modified version of the "PTC ADAPT Self-Test
# Program". The mods relate to those points where (due
# partially to inadequate or nonexistent documentation),
# I absolutely could not figure out what the functionality
# of certain PIO or CIO instructions was, and hence could
# not implement the corresponding features in the emulator
# in such a way as to make the test pass. The error traps
# for those cases are commented out, replaced typically by
# "TNZ *+1" or similar (so that all code and variable
# addresses remain the same), and marked "FIX_EMULATOR".
# Assembler: yaASM.py --ptc [--past-bugs]
# Contact: Ron Burkey <info@sandroid.org>.
# Octals: (Transcribed from scans) PTC-ADAPT-Self-Test-Program.lvdc
# Web page: http://www.ibiblio.org/apollo/LVDC.html#PTC_ADAPT_Self-Test_Program
# Page scans: http://www.ibiblio.org/apollo/ScansForConversion/PTC%20ADAPT%20Self-Test%20Program.zip
# Executable: https://github.com/virtualagc/virtualagc/blob/master/PTC-ADAPT-Self-Test-Program/PTC-ADAPT-Self-Test-Program.tsv
# Documentation:http://www.ibiblio.org/apollo/Documents/19730064346_1973064346.pdf,
# particularly Chapter 7 ("Calibration"), from which the page scans and
# executable (assembled octals) mentioned above were taken. Figure 7-12
# is this complete software in flowchart form. The web page linked above
# also covers known errors in the documentation.
# Mod history: 2020-06-11 RSB Began adapting from the full PTC ADAPT
# Self-Test Program.
# PAGE 1, SEQUENCE 20-580
* TAPE 6001236
DOG 0,17,0
BSS 15
H17P2 HPC L17P2
ZERO OCT 000000000
BB OCT 000000010
H2P1 HPC L2P1
H9P3 HPC L9P3
H43P2 HPC L43P2
H8P1A HPC L8P1
H95P1 HPC L95P1
H95P7 HPC L95P7
HJAJ5 HPC JAJ5
HJAJ5B HPC JAJ5B
K1 OCT 000000002
K77 OCT 777777776
K1303 OCT 130300000
K324 OCT 000001520
KS1 OCT 002000000
KS2 OCT 000000100
KX1 OCT 000777776
KX2 OCT 270000000
KX3 OCT 260000000
KX4 OCT 250000000
KX5 OCT 240000000
KX6 OCT 777000000
KX7 OCT 000037740
KX8 OCT 777740036
LC2 OCT 000000000
LC3 OCT 000000000
LC5 OCT 000000000
LC7 OCT 000000000
LC8 OCT 000000000
LCR2 OCT 000000000
LCR3 OCT 000000000
LCR4 OCT 000000000
LCR5 OCT 000000000
LCR6 OCT 000000000
LCR7 OCT 000000000
LCR8 OCT 000000000
LCR9 OCT 000000000
LCR10 OCT 000000000
LCR11 OCT 000000000
LCR12 OCT 000000000
VAR1 OCT 000000000
VAR2 OCT 000000000
VAR3 OCT 000000000
VAR4 OCT 000000000
VAR5 OCT 000000000
INTIND OCT 000000000
TEMP OCT 000000000
TEMP1 OCT 000000000
STOP OCT 000000000
CTR OCT 000000000
CTR3 OCT 000000000
HRTRN OCT 000000000
CHAR OCT 610000000 A
# PAGE 2, SEQUENCE 590-1150
OCT 620000000 B
OCT 630000000 C
OCT 640000000 D
OCT 650000000 E
OCT 660000000 F
OCT 670000000 G
C7 OCT 700000000 H
OCT 710000000 I
C9 OCT 410000000 J
OCT 420000000 K
OCT 430000000 L
OCT 440000000 M
OCT 450000000 N
OCT 460000000 O
OCT 470000000 P
OCT 500000000 Q
OCT 510000000 R
OCT 220000000 S
OCT 230000000 T
OCT 240000000 U
OCT 250000000 V
OCT 260000000 W
OCT 270000000 X
OCT 300000000 Y
OCT 310101010 Z WITH NO CHECK BITS
C26 OCT 010000000 1
C27 OCT 020000000 2
C28 OCT 030000000 3
C29 OCT 040000000 4
OCT 050000000 5
C31 OCT 060000000 6
OCT 070000000 7
OCT 100000000 8
OCT 110000000 9
OCT 120000000 0
C36 OCT 130000000 SPECIAL CHARS
C37 OCT 200000000
C38 OCT 210000000
OCT 330000000
C40 OCT 400000000
OCT 530000000
C42 OCT 600000000
OCT 730000000
OCT 000000000 SPACE
C45 OCT 140000000 UPPER CASE
OCT 150000000
OCT 160000000
OCT 170000000
OCT 320000000
OCT 340000000
OCT 350000000
OCT 360000000
OCT 370000000
OCT 520000000
OCT 540000000
OCT 550000000
OCT 560000000
# PAGE 3, SEQUENCE 1160-1480
OCT 570000000
OCT 720000000
C60 OCT 740000000
OCT 750000000
OCT 760000000
OCT 770000000
C64 OCT 110000000 OCTAL 1
OCT 210000000 OCTAL 2
OCT 310000000 OCTAL 3
OCT 410000000 OCTAL 4
OCT 510000000 OCTAL 5
OCT 610000000 OCTAL 6
OCT 710000000 OCTAL 7
OCT 010000000 OCTAL 0
OCT 050000000 DECIMAL 1
OCT 110000000 DECIMAL 2
OCT 150000000 DECIMAL 3
OCT 210000000 DECIMAL 4
OCT 250000000 DECIMAL 5
OCT 310000000 DECIMAL 6
OCT 350000000 DECIMAL 7
OCT 410000000 DECIMAL 8
OCT 450000000 DECIMAL 9
OCT 510000000 DECIMAL 0
OCT 400000000 SPACE - CNTRL OPNS
OCT 010000000 TAB
OCT 020000000 CARRIAGE RETURN
OCT 040000000 INDEX
OCT 100000000 RED
OCT 200000000 BLACK
LINE1 BCI ^ROUTINE 7, EXERCISE TYPEWRITER$
LINE2 BCI ^TYPE ALL ALPHANUMERIC IN BLACK$
LINE3 BCI ^ABCDEFGHIJKLMNOPQRSTUVWXYZ,1234567890$
# PAGE 4, SEQUENCE 1490-1620
LINE4 OCT 141516170 SPECIAL CHARACTERS
OCT 323435360
OCT 372052210
OCT 565772740
OCT 757677130
OCT 543355400
OCT 536073000
DOG 0,17,300
LINE5 BCI ^TYPE OCTAL CHARACTERS$
LINE5A OCT 012345670
LINE6 BCI ^TYPE DECIMAL INTEGERS IN RED$
LINE6A OCT 044321260
LINE6B OCT 361150000
H30P2A HPC L30P2A
# PAGE 5, SEQUENCE 1640-2200
ORG ,,,,,13,0
H5P3 HPC L5P3
H5P4 HPC L5P4
H5P5 HPC L5P5
H5P6 HPC L5P6
H5P7 HPC L5P7
H6P1 HPC L6P1
H6P2 HPC L6P2
H6P3 HPC L6P3
H6P4 HPC L6P4
H6P5 HPC L6P5
H6P6 HPC L6P6
H6P7 HPC L6P7
H6P8 HPC L6P8
H6P9 HPC L6P9
H6P10 HPC L6P10
H6P11 HPC L6P11
H6P12 HPC L6P12
H6P13 HPC L6P13
H6P14 HPC L6P14
H6P15 HPC L6P15
H6P16 HPC L6P16
H6P17 HPC L6P17
H6P18 HPC L6P18
H6P19 HPC L6P19
H6P20 HPC L6P20
H6P21 HPC L6P21
H6P22 HPC L6P22
H6P23 HPC L6P23
H7P1 HPC L7P1
H7P2 HPC L7P2
H7P3 HPC L7P3
H7P4 HPC L7P4
H7P5 HPC L7P5
H7P6 HPC L7P6
H7P7 HPC L7P7
H7P8 HPC L7P8
H7P9 HPC L7P9
H7P10 HPC L7P10
H7P11 HPC L7P11
H7P12 HPC L7P12
H7P13 HPC L7P13
H7P14 HPC L7P14
H7P15 HPC L7P15
H7P16 HPC L7P16
H7P17 HPC L7P17
H7P18 HPC L7P18
H7P19 HPC L7P19
H7P20 HPC L7P20
H7P21 HPC L7P21
H7P22 HPC L7P22
H7P23 HPC L7P23
H7P24 HPC L7P24
H7P25 HPC L7P25
H7P26 HPC L7P26
H7P27 HPC L7P27
H7P28 HPC L7P28
# PAGE 6, SEQUENCE 2210-2530
H7P29 HPC L7P29
H7P30 HPC L7P30
H7P31 HPC L7P31
H7P32 HPC L7P32
H7P33 HPC L7P33
H7P34 HPC L7P34
H7P35 HPC L7P35
H7P36 HPC L7P36
H7P37 HPC L7P37
H7P38 HPC L7P38
H7P39 HPC L7P39
H7P40 HPC L7P40
H7P41 HPC L7P41
H7P42 HPC L7P42
H7P43 HPC L7P43
H7P44 HPC L7P44
H7P45 HPC L7P45
H7P46 HPC L7P46
H7P47 HPC L7P47
H7P48 HPC L7P48
H7P49 HPC L7P49
H7P50 HPC L7P50
H7P51 HPC L7P51
H7P52 HPC L7P52
H7P53 HPC L7P53
H7P54 HPC L7P54
H7P54B HPC L7P54B
H8P1 HPC L8P1
H8P2 HPC L8P2
H8P3 HPC L8P3
H8P4 HPC L8P4
H8P5 HPC L8P5
H8P6 HPC L8P6
# PAGE 7, SEQUENCE 2550-3000
# This is the entry point for the program at power-up.
# Note that there's already a bug ... or at least an
# element of unnecessary confusion! Because of the
# preceding ORG statement on page 5, the assembler
# believes that the current data sector is 0-13, and
# it will therefore look in that memory sector when it
# accesses variables. On the other hand, the CPU has
# no way of knowing at runtime what the assembler
# believes, and will instead believe that the current
# data sector is 0-00. Perhaps by design, however,
# the initial instructions of the program access variables
# (ZERO, INTIND, STOP, CTR, LC8) that are in residual
# memory, and thus are accessible regardless of
# whether the assembler and the CPU agree as to which
# memory sector is currently selected. The 6th
# instruction executed, "CDS 1,13" puts the assembler
# and CPU into agreement for subsequently-encountered
# variables. -- RSB 2020
* PROGRAM ENTRANCE.
L1P1 CLA ZERO
STO INTIND
STO STOP
STO CTR
STO LC8
CDS 1,13
STO TIME
STO CSCTR
STO DDCTR
CDS 0,13
CIO 214
TMI L1P1A
TRA L2P1
L1P1A TRA L1P1A1
L2P1 CLA VAR3
ADD =O000000002
STO VAR3
CIO 204
CLA ZERO
STO VAR4
STO VAR5
CIO 214 ASWT
ADD K1
SHL 1
STO LCR1 A1
SHL 1
STO LCR2 A2
SHL 1
STO LCR3 A3
SHL 1
STO LCR4 A4
SHL 1
STO LCR5 A5
SHL 1
STO LCR6 A6
SHL 1
STO LCR7 A7
SHL 1
STO LCR8 A8
SHL 1
STO LCR9 A9
SHL 1
STO LCR10 A10
SHL 1
STO LCR11 A11
# PAGE 8, SEQUENCE 3100-3520
SHL 1
STO LCR12 A12
SHL 1
STO LC1 A13
SHL 1
STO LC2 A14
SHL 1
STO LC3 A15
SHL 1
TMI L2P2 A16
TRA L3P1
L2P2 TRA L97P1
L3P1 CLA LC1
TMI *+2
TRA L5P1
CLA LCR1
TMI L4P1
CLA LCR2
TMI L4P2
CLA LCR3
TMI L4P3
CLA LCR4
TMI L4P4
CLA LCR5
TMI L4P5
CLA LCR6
TMI L4P6
CLA LCR7
TMI L4P7
CLA LCR8
TMI L4P8
CLA LCR9
TMI L4CP1
CLA LCR10
TMI L4CP2
CLA LCR11
TMI L4CP3
TRA L2P1
L4P1 CLA ZERO
STO LCR2
TRA L5P2 TO ROUTINE 1
L4P2 CLA ZERO
STO LCR3
TRA L6P2 TO ROUTINE 2
L4P3 CLA ZERO
STO LCR4
TRA L9P2
L4P4 CLA ZERO
STO LCR5
TRA L20P2
L4P5 CLA ZERO
# PAGE 9, SEQUENCE 3530-4090
STO LCR6
TRA L29P2
L4P6 CLA ZERO
STO LCR7
TRA L45P2
L4P7 CLA ZERO
STO LCR8
TRA L50P2
L4P8 CLA ZERO
STO LCR9
TRA L60P2
L4CP1 CLA ZERO
STO LCR10
TRA JAB1
L4CP2 CLA ZERO
STO LCR11
TRA MAB1
L4CP3 CLA ZERO
STO LCR12
TRA NAB1
L5P1 CLA LCR1
TMI L5P2
TRA L6P1
* BEGINNING OF ROUTINE ONE
* CHECK COMPUTER FOR ABILITY TO HOP TO ALL SECTORS.
L5P2 HOP HP1
HP1 HPC L5P2A
* SECTOR 1.
ORG ,1,,2,,1,
L5P2A HOP HP2
HP2 HPC L5P2B
* SECTOR 2.
ORG ,2,1,0,,2,1
L5P2B HOP HP3
HP3 HPC L5P2C
* SECTOR 3.
ORG ,3,,376,,3,
L5P2C HOP HP4
HP4 HPC L5P2D
* SECTOR 4.
ORG ,4,,52,,4,
L5P2D HOP HP5
HP5 HPC L5P2E
* SECTOR 5.
ORG ,5,,3,,5,10
L5P2E HOP HP6
HP6 HPC L5P2F
* SECTOR 6.
ORG ,6,,0,,16,365
L5P2F HOP HP7
HP7 HPC L5P2G
* SECTOR 7.
ORG ,7,,177,,16,
L5P2G HOP HP8
HP8 HPC L5P2H
* SECTOR 10.
ORG ,10,1,77,,16,
# PAGE 10, SEQUENCE 4100-4650
L5P2H HOP HP9
HP9 HPC L5P2I
* SECTOR 11.
ORG ,11,1,257,,16,
L5P2I HOP HP10
HP10 HPC L5P2J
* SECTOR 12.
ORG ,12,,,,16,
L5P2J HOP HP11
HP11 HPC L5P2K
* SECTOR 13.
ORG ,13,1,376,,16,
L5P2K HOP HP12
HP12 HPC L5P2L
* SECTOR 14.
ORG ,14,,30,,16,
L5P2L HOP HP13
HP13 HPC L5P2M
* SECTOR 15.
ORG ,15,,376,,16,
L5P2M HOP HP14
HP14 HPC L5P2N
* SECTOR 16.
ORG ,16,,0,,16,376
L5P2N HOP HP15
HP15 HPC L5P2P
* SECTOR 17.
ORG ,17,1,277,,16,
# The following line appears in the original assembly listing,
# but was generated by the assembler rather than being source
# code. It is thus commented-out here. However, I've been
# unable to figure out how to get the assembler to automatically
# generate the necessary transfer and insert it here. So
# the two lines following the comment have been added to this
# source file to produce the necessary effect. They should be
# removed after I figure how to reproduce the correct behavior
# directly within the assembler.
# TRA** GENERATED TRANSFER
TRA L5P2P # workaround
ORG ,17,1,322,,16, # workaround
L5P2P HOP HP16
HP16 HPC L5P2Q
* MEMORY MODULE 1
* SECTOR 0 MM1
ORG 1,,,,1,,
L5P2Q HOP HP17
HP17 HPC L5P2R
* SECTOR 1 MM1
ORG 1,1,1,1,1,1,2
L5P2R HOP HP18
HP18 HPC L5P2S
* SECTOR 2 MM1
ORG 1,2,,2,1,2,3
L5P2S HOP HP19
HP19 HPC L5P2T
* SECTOR 3 MM1
ORG 1,3,,3,1,3,4
L5P2T HOP HP20
HP20 HPC L5P2U
* SECTOR 4 MM1
ORG 1,4,,4,1,4,5
L5P2U HOP HP21
HP21 HPC L5P2V
* SECTOR 5 MM1
ORG 1,5,1,5,1,5,6
L5P2V HOP HP22
HP22 HPC L5P2W
* SECTOR 6 MM1
# PAGE 11, SEQUENCE 4660-5040
ORG 1,6,,60,1,6,7
L5P2W HOP HP23
HP23 HPC L5P2X
* SECTOR 7
ORG 1,7,,37,1,7,17
L5P2X HOP HP24
HP24 HPC L5P2Y
* SECTOR 10 MM1
ORG 1,10,,100,1,10,27
L5P2Y HOP HP25
HP25 HPC L5P2Z
* SECTOR 11 MM1
ORG 1,11,,200,1,11,37
L5P2Z HOP HP26
HP26 HPC L5P2AA
* SECTOR 12 MM1
ORG 1,12,,376,1,12,377
L5P2AA HOP HP27
HP27 HPC L5P2BB
* SECTOR 13 MM1
ORG 1,13,,376,1,13,377
L5P2BB HOP HP28
HP28 HPC L5P2CC
* SECTOR 14 MM1
ORG 1,14,,177,1,14,377
L5P2CC HOP HP29
HP29 HPC L5P2DD
* SECTOR 15 MM1
ORG 1,15,,7,1,15,177
L5P2DD HOP HP30
HP30 HPC L5P2EE
* SECTOR 16 MM1
ORG 1,16,1,,1,16,100
L5P2EE HOP HP31
HP31 HPC L5P2FF
* SECTOR 17 MM1
ORG 1,17,1,375,1,17,77
L5P2FF HOP HP32
HP32 HPC L5P3
# PAGE 12, SEQUENCE 5060-5490
* BEGIN CHECK OF TRANSFER CLASS INSTRUCTIONS.
ORG ,,,373,,13,
TRA L5P7A
* TEST TRA TO SYLL 1
ORG ,,1,373,,13,
L5P7 CLA =O500000000
TRA L5P7A
* TEST TMI INSTRUCTION.
ORG ,,,170,,13,
L5P3 CLA H5P3
STO VAR1
CLA H5P4
STO VAR2
CLA =O400000000
TMI L5P4
HOP H95P1
* TEST TNZ INSTRUCTION.
L5P4 CLA H5P4
STO VAR1
CLA H5P5
STO VAR2
CLA =O000000002
TNZ L5P5
HOP H95P1
* TEST TMI WITH CLEARED ACCUMULATOR.
L5P5 CLA H5P5
STO VAR1
CLA H5P6
STO VAR2
CLA =O000000000
TMI L15P1L
TRA L5P6
HOP H95P1
* TEST TNZ WITH CLEARED ACCUMULATOR.
L5P6 CLA H5P6
STO VAR1
CLA H5P7
STO VAR2
CLA =O000000000
TNZ L15P1L
TRA L5P7
HOP H95P1
L5P7A TMI L6P1
L15P1L TRA L95P1
# PAGE 13, SEQUENCE 5510-5810
* BEGINNING OF ROUTINE TWO
* OPERATION OF STO - ALL ONES.
L6P1 CLA LCR2
TMI L6P2 TO ROUTINE 2
TNZ L6P1A
TRA L2P1
L6P1A TRA L9P1
L6P2 CLA H6P2
STO VAR1
CLA H6P3
STO VAR2
CLA =O777777776
TNZ *+2
TRA L95P1
STO TEMP1
CLA =O000000000
CLA TEMP1
TNZ L6P2A
TRA L95P1
L6P2A ADD =O000000002
TNZ L15P1K
* CHECK STO WITH ALL ZEROS.
L6P3 CLA H6P3
STO VAR1
CLA H6P4
STO VAR2
CLA =O000000000
STO TEMP1
CLA =O777777776
CLA TEMP1
TNZ L15P1K
# PAGE 14, SEQUENCE 5830-6390
* CAN ACCUMULATOR BE FILLED BY ADD.
L6P4 CLA H6P4
STO VAR1
CLA H6P5
STO VAR2
CLA =O000000000
ADD =O777777776
TNZ *+2
TRA L15P1K
SUB =O777777776
TNZ L15P1K
* CAN ACCUMULATOR BE CHANGED BY ADDING ZERO
L6P5 CLA H6P5
STO VAR1
CLA H6P6
STO VAR2
CLA =O777777776
ADD =O000000000
SUB =O777777776
TNZ L15P1K
* CAN ACCUMULATOR BE CLEARED BY ADD.
L6P6 CLA H6P6
STO VAR1
CLA H6P7
STO VAR2
CLA =O777777776
ADD =O000000002
TNZ L15P1K
* SAME AS L5P5 EXCEPT CONSTANTS REVERSED.
L6P7 CLA H6P7
STO VAR1
CLA H6P8
STO VAR2
CLA =O000000002
ADD =O777777776
TNZ L15P1K
TRA L6P8
* CHECK FOR CHANGE OF SIGN BIT.
L6P8 CLA H6P8
STO VAR1
CLA H6P9
STO VAR2
CLA =O200000000
ADD =O200000000
TMI L6P9
TRA L15P1K
* SAME AS L5P7.
L6P9 CLA H6P9
STO VAR1
CLA H6P10
STO VAR2
CLA =O400000000
ADD =O400000000
TMI L15P1K
* ALL BIT COMBINATIONS ON ADD
L6P10 CLA H6P10
STO VAR1
# PAGE 15, SEQUENCE 6400-6450
CLA H6P11
STO VAR2
CLA =O252642550
ADD =O107301660
SUB =O362144430
TNZ L15P1K
# PAGE 16, SEQUENCE 6470-7020
* CHECK SIMPLE SUBTRACTION.
L6P11 CLA H6P11
STO VAR1
CLA H6P12
STO VAR2
CLA =O400000000
SUB =O400000000
TNZ L15P1K
* CHECK SUBTRACTION OF LOW ORDER BIT
L6P12 CLA H6P12
STO VAR1
CLA H6P13
STO VAR2
CLA =O000000002
SUB =O000000002
TNZ L15P1K
# The following line appears in the original assembly listing,
# but was generated by the assembler rather than being source
# code. It is thus commented-out here. I can't yet get the
# modern assembler to auto-insert the TRA** here, so the
# 2 lines after the commented-out TRA** have been added
# as a workaround.
# TRA** GENERATED TRANSFER
TRA WKRND1 # workaround
ORG 0,0,0,374,0,13, # workaround
WKRND1 TRA L6P13 # the lhs is a workaround
* SUBTRACT ALL ODD BITS.
ORG ,,1,,,13,
L6P13 CLA H6P13
STO VAR1
CLA H6P14
STO VAR2
CLA =O525252524
SUB =O525252524
TNZ L15P1K
* SUBTRACT ALL EVEN BITS.
L6P14 CLA H6P14
STO VAR1
CLA H6P15
STO VAR2
CLA =O252525252
SUB =O252525252
TNZ L15P1K
* FILL ACCUMULATOR WITH SUBTRACT.
L6P15 CLA H6P15
STO VAR1
CLA H6P16
STO VAR2
CLA =O000000000
SUB =O000000002
SUB =O777777776
TNZ L15P1K
* CHECK SUBTRACT ZERO.
L6P16 CLA H6P16
STO VAR1
CLA H6P17
STO VAR2
CLA =O000000000
SUB =O000000000
TNZ L15P1K
* SUB - ALL COMBINATIONS
L6P17 CLA H6P17
STO VAR1
CLA H6P18
STO VAR2
# PAGE 17, SEQUENCE 7030-7550
CLA =O046453224
SUB =O114722350
SUB =O731530654
TNZ L15P1K
* CHECK AND FOR CLEARING ACCUMULATOR.
L6P18 CLA H6P18
STO VAR1
CLA H6P19
STO VAR2
CLA =O525252524
AND =O252525252
TNZ L15P1K
* CHECK FOR EVEN BITS.
L6P19 CLA H6P19
STO VAR1
CLA H6P20
STO VAR2
CLA =O252525252
AND =O525252524
TNZ L15P1K
* CHECK FOR ABILITY TO RETAIN ACCUMULATOR
L6P20 CLA H6P20
STO VAR1
CLA H6P21
STO VAR2
CLA =O777777776
AND =O777777776
SUB =O777777776
TNZ L15P1K
* CHECK AND ZERO TO CHANGE ACCUMULATOR
L6P21 CLA H6P21
STO VAR1
CLA H6P22
STO VAR2
CLA =O000000000
AND =O000000000
TNZ L15P1K
* CHECK AND ZERO TO CLEAR ACCUMULATOR
L6P22 CLA H6P22
STO VAR1
CLA H6P23
STO VAR2
CLA =O777777776
AND =O000000000
TNZ L15P1K
* CHECK AND OF ALL BITS.
L6P23 CLA H6P23
STO VAR1
CLA H7P1
STO VAR2
CLA =O000000000
AND =O777777776
TNZ L15P1K
# PAGE 18, SEQUENCE 7570-8130
* CHECK XOR OF ALL BITS.
L7P1 CLA H7P1
STO VAR1
CLA H7P2
STO VAR2
CLA =O777777776
XOR =O777777776
TNZ L15P1K
* CHECK XOR WITH ALL ZEROS.
L7P2 CLA H7P2
STO VAR1
CLA H7P3
STO VAR2
CLA =O000000000
XOR =O000000000
TNZ L15P1K
* CHECK SIGN BITS.
L7P3 CLA H7P3
STO VAR1
CLA H7P4
STO VAR2
CLA =O400000000
XOR =O400000000
TNZ L15P1K
* CHECK ALL BUT SIGN BITS.
L7P4 CLA H7P4
STO VAR1
CLA H7P5
STO VAR2
CLA =O377777776
XOR =O377777776
TNZ L15P1K
* CHECK LOW ORDER BITS.
L7P5 CLA H7P5
STO VAR1
CLA H7P6
STO VAR2
CLA =O000000002
XOR =O000000002
TNZ L15P1K
* CHECK LOW ORDER BIT WITH ZEROS.
L7P6 CLA H7P6
STO VAR1
CLA H7P7
STO VAR2
CLA =O777777774
XOR =O777777774
TNZ L15P1K
TRA L7P7
L15P1K TRA L95P1
* CHECK ALL ODD BITS
L7P7 CLA H7P7
STO VAR1
CLA H7P8
STO VAR2
CLA =O525252524
XOR =O525252524
# PAGE 19, SEQUENCE 8140-8700
TNZ L15P1K
* CHECK ALL EVEN BITS
L7P8 CLA H7P8
STO VAR1
CLA H7P9
STO VAR2
CLA =O252525252
XOR =O252525252
TNZ L15P1K
* FILL ACCUMULATOR WITH XOR.
L7P9 CLA H7P9
STO VAR1
CLA H7P10
STO VAR2
CLA =O777777776
XOR =O000000000
SUB =O777777776
TNZ L15P1K
* SAME AS L7P9
L7P10 CLA H7P10
STO VAR1
CLA H7P11
STO VAR2
CLA =O000000000
XOR =O777777776
SUB =O777777776
TNZ L15P1K
* SAME AS L7P9 WITH ODD BITS
L7P11 CLA H7P11
STO VAR1
CLA H7P12
STO VAR2
CLA =O525252524
XOR =O252525252
SUB =O777777776
TNZ L15P1K
* SAME AS L7P9 WITH EVEN BITS
L7P12 CLA H7P12
STO VAR1
CLA H7P13
STO VAR2
CLA =O252525252
XOR =O525252524
SUB =O777777776
TNZ L15P1K
* CHECK RSU
L7P13 CLA H7P13
STO VAR1
CLA H7P14
STO VAR2
CLA =O777777776
RSU =O777777774
SUB =O777777776
TNZ L15P1K
* CHECK RSU
L7P14 CLA H7P14
STO VAR1
# PAGE 20, SEQUENCE 8710-9260
CLA H7P15
STO VAR2
CLA =O000000002
RSU =O000000000
SUB =O777777776
TNZ L15P1K
* CHECK RSU
L7P15 CLA H7P15
STO VAR1
CLA H7P16
STO VAR2
CLA =O777777776
RSU =O777777776
TNZ L15P1K
* CHECK RSU
L7P16 CLA H7P16
STO VAR1
CLA H7P17
STO VAR2
CLA =O000000000
RSU =O000000000
TNZ L15P1K
* CHECK RSU TO FILL AND CLEAR ACC.
L7P17 CLA H7P17
STO VAR1
CLA H7P18
STO VAR2
CLA =O777777776
RSU =O000000000
SUB =O000000002
TNZ L15P1K
* CHECK RSU
L7P18 CLA H7P18
STO VAR1
CLA H7P19
STO VAR2
CLA =O331033100
RSU =O265026500
SUB =O733773400
TNZ L15P1K
* BEGIN CHECK OF SHIFT INSTRUCTION.
* SHIFT OUT OF SIGN BIT.
L7P19 CLA H7P19
STO VAR1
CLA H7P20
STO VAR2
CLA =O400000000
SHL 1
TNZ L15P1K
* SHIFT THROUGH SIGN BIT.
L7P20 CLA H7P20
STO VAR1
CLA H7P21
STO VAR2
CLA =O200000000
# PAGE 21, SEQUENCE 9270-9770
SHL 2
TNZ L15P1K
* CHECK SHIFT LEFT ONE OF ALL ODD BITS.
L7P21 CLA H7P21
STO VAR1
CLA H7P22
STO VAR2
CLA =O525252524
SHL 1
SUB =O252525250
TNZ L15P1K
* CHECK
L7P22 CLA H7P22
STO VAR1
CLA H7P23
STO VAR2
CLA =O525252524
SHL 2
SUB =O525252520
TNZ L15P1K
TRA L7P23
* CHECK SHIFT LEFT ONE OF ALL EVEN BITS.
ORG ,1,,3,,13,
L7P23 CLA H7P23
STO VAR1
CLA H7P24
STO VAR2
CLA =O252525252
SHL 1
SUB =O525252524
TNZ L15P1J
* CHECK SHIFT LEFT TWO OF ALL EVEN BITS.
L7P24 CLA H7P24
STO VAR1
CLA H7P25
STO VAR2
CLA =O252525252
SHL 2
SUB =O252525250
TNZ L15P1J
* CHECK SHIFT LEFT ONE OF ALL BITS.
L7P25 CLA H7P25
STO VAR1
CLA H7P26
STO VAR2
CLA =O777777776
SHL 1
SUB =O777777774
TNZ L15P1J
* CHECK SHIFT LEFT TWO OF ALL BITS.
L7P26 CLA H7P26
# PAGE 22, SEQUENCE 9780-10000
STO VAR1
CLA H7P27
STO VAR2
CLA =O777777776
SHL 2
SUB =O777777770
TNZ L15P1J
* CHECK CHECK SHIFT LEFT ONE OF ALL ZEROS.
L7P27 CLA H7P27
STO VAR1
CLA H7P28
STO VAR2
CLA =O000000000
SHL 1
TNZ L15P1J
* CHECK SHIFT LEFT TWO OF ALL ZEROS.
L7P28 CLA H7P28
STO VAR1
CLA H7P29
STO VAR2
CLA =O000000000
SHL 2
TNZ L15P1J
# PAGE 23, SEQUENCE 10020-10490
* CHECK SHIFT BIT LEFT THROUGH ALL POSITIONS
L7P29 CLA H7P29
STO VAR1
CLA H7P30
STO VAR2
CLA =O000000002
SHL 25
SUB =O400000000
TNZ L15P1J
* CHECK SHL3
L7P30 CLA H7P30
STO VAR1
CLA H7P31
STO VAR2
CLA =O042104212
SHL 3
XOR =O421042120
TNZ L15P1H
* CHECK SHL4
L7P31 CLA H7P31
STO VAR1
CLA H7P32
STO VAR2
CLA =O020410206
SHL 4
XOR =O410204140
TNZ L15P1H
* CHECK SHL5
L7P32 CLA H7P32
STO VAR1
CLA H7P33
STO VAR2
CLA =O010101012
SHL 5
XOR =O404040500
TNZ L15P1H
* CHECK SHL6
L7P33 CLA H7P33
STO VAR1
CLA H7P34
STO VAR2
CLA =O004020102
SHL 6
XOR =O402010200
TNZ L15P1H
* CHECK SHL6 EVEN BITS
L7P34 CLA H7P34
STO VAR1
# PAGE 24, SEQUENCE 10500-11000
CLA H7P35
STO VAR2
CLA =O252525252
SHL 6
SUB =O252525200
TNZ L15P1H
* CHECK SHL6 ODD BITS
L7P35 CLA H7P35
STO VAR1
CLA H7P36
STO VAR2
CLA =O525252524
SHL 6
SUB =O525252400
TNZ L15P1H
* SHIFT OUT OF LOW ORDER BIT.
L7P36 CLA H7P36
STO VAR1
CLA H7P37
STO VAR2
CLA =O000000002
SHR 1
TNZ L15P1J
* SHIFT THROUGH LOW ORDER BIT.
L7P37 CLA H7P37
STO VAR1
CLA H7P38
STO VAR2
CLA =O000000004
SHR 2
TNZ L15P1J
* CHECK SHIFT RIGHT ONE OF ALL ODD BITS.
L7P38 CLA H7P38
STO VAR1
CLA H7P39
STO VAR2
CLA =O525252524
SHR 1
SUB =O652525252
TNZ L15P1J
* CHECK SHIFT RIGHT TWO OF ALL ODD BITS.
L7P39 CLA H7P39
STO VAR1
CLA H7P40
STO VAR2
CLA =O525252524
SHR 2
SUB =O725252524
TNZ L15P1J
* CHECK SHIFT RIGHT ONE OF ALL EVEN BITS.
L7P40 CLA H7P40
# PAGE 25, SEQUENCE 11010-11520
STO VAR1
CLA H7P41
STO VAR2
CLA =O252525252
SHR 1
SUB =O125252524
TNZ L15P1J
* CHECK SHIFT RIGHT TWO OF ALL EVEN BITS.
L7P41 CLA H7P41
STO VAR1
CLA H7P42
STO VAR2
CLA =O252525252
SHR 2
SUB =O052525252
TNZ L15P1J
TRA L7P42
L15P1J TRA L95P1
L15P1H SYN L15P1J
* CHECK SHIFT RIGHT ONE OF ALL BITS.
L7P42 CLA H7P42
STO VAR1
CLA H7P43
STO VAR2
CLA =O777777776
SHR 1
SUB =O777777776
TNZ L15P1J
* CHECK SHIFT RIGHT TWO OF ALL BITS.
L7P43 CLA H7P43
STO VAR1
CLA H7P44
STO VAR2
CLA =O777777776
SHR 2
SUB =O777777776
TNZ L15P1J
* CHECK SHIFT RIGHT ONE OF ALL ZEROS.
L7P44 CLA H7P44
STO VAR1
CLA H7P45
STO VAR2
CLA =O000000000
SHR 1
TNZ L15P1J
* CHECK SHIFT RIGHT TWO OF ALL ZEROS.
L7P45 CLA H7P45
STO VAR1
CLA H7P46
STO VAR2
CLA =O000000000
# PAGE 26, SEQUENCE 11530-11990
SHR 2
TNZ L15P1J
* SHIFT BIT RIGHT THROUGH ALL POSITIONS.
L7P46 CLA H7P46
STO VAR1
CLA H7P47
STO VAR2
CLA =O400000000
SHR 25
SUB =O777777776
TNZ L15P1J
* CHECK SHR3
L7P47 CLA H7P47
STO VAR1
CLA H7P48
STO VAR2
CLA =O210421042
SHR 3
XOR =O021042104
TNZ L15P1H
* CHECK SHR4
L7P48 CLA H7P48
STO VAR1
CLA H7P49
STO VAR2
CLA =O214102040
SHR 4
XOR =O010604102
TNZ L15P1H
* CHECK SHR5
L7P49 CLA H7P49
STO VAR1
CLA H7P50
STO VAR2
CLA =O202020200
SHR 5
XOR =O004040404
TNZ L15P1H
* CHECK SHR6
L7P50 CLA H7P50
STO VAR1
CLA H7P51
STO VAR2
CLA =O201004220
SHR 6
XOR =O002010042
TNZ L15P1H
# PAGE 27, SEQUENCE 12000-12490
* CHECK SHR6 EVEN BITS
L7P51 CLA H7P51
STO VAR1
CLA H7P52
STO VAR2
CLA =O252525252
SHR 6
SUB =O002525252
TNZ L15P1H
* CHECK SHR6 ODD BITS
L7P52 CLA H7P52
STO VAR1
CLA H7P53
STO VAR2
CLA =O525252524
SHR 6
SUB =O775252524
TNZ L15P1H
TRA L7P53
* CHECK CDS
ORG ,1,1,2,,13,
L7P53 CLA H7P53
STO VAR1
CLA H7P54
STO VAR2
CLA =O000000000
CDS 1,07
CLA KMA
CDS 0,10
TMI L15P1T
SHL 1
TMI *+2
L15P1T TRA L15P1H
CLA KMB
TMI *+2
TRA L15P1T
SHL 2
TMI *+2
TRA L15P1T
SHL 1
TNZ L15P1T
CDS 0,0
CLA KMR
CDS 0,13
SHL 2
TMI L15P1H
TNZ *+2
TRA L15P1H
SHL 2
TNZ L15P1H
# PAGE 28, SEQUENCE 12500-13060
* CHECK HOP SAVE CONSTANT
TRA L7P54
ORG ,3,,17,,13,
L7P54 STO 776
CLA H7P54
STO VAR1
CLA H7P54B
# The following line was not present in the original code. It is
# here as a workaround because I've been unable to figure out how
# to reproduce one of the original assembler's bugs in the modern
# assembler.
DOG 0,13,140 # workaround
H7P55B HPC L7P55
L7P54A STO VAR2
CLA 776
XOR H8P1A
TNZ L95P1A
L7P54B HOP H7P55B
L95P1A HOP H95P1
ORG 1,17,1,352,1,17,
L7P55 STO 777
CLA H7P55
STO VAR1
CLA H8P1A
L7P55A STO VAR2
CLA 777
XOR H95P1A
H95P1A HPC L95P1A
TNZ L15P1M
HOP H8P1A
H7P55 HPC L7P55
L15P1M TRA L95P1
ORG ,1,1,40,,13,
* CHECK AFFECT OF PRS 775 ON ACCUMULATOR
L8P1 CLA H8P1
STO VAR1
CLA H8P2
STO VAR2
CLA =O123456702
PRS 775
XOR =O123456702
TNZ L15P1N
* CHECK AFFECT OF PRS 774 ON ACCUMULATOR
L8P2 CLA H8P2
STO VAR1
CLA H8P3
STO VAR2
CLA =O765432106
PRS 774
XOR =O765432106
TNZ L15P1N
* CHECK AFFECT OF PRS MEMORY ON ACCUMULATOR
L8P3 CLA H8P3
STO VAR1
CLA H8P4
STO VAR2
CLA =O777777776
# PAGE 29, SEQUENCE 13070-13630
PRS H8P3
XOR H8P3
TNZ L15P1N
* CHECK AFFECT OF CIO 120 ON ACCUMULATOR
L8P4 CLA H8P4
STO VAR1
CLA H8P5
STO VAR2
CLA =O777777776
CIO 120
XOR =O777777776
TNZ L15P1N
* SAME AS ABOVE FOR CIO 124
L8P5 CLA H8P5
STO VAR1
CLA H8P6
# The following line appears to me to be a bug in the original source
# code, and that it should be VAR2 rather than VAR1.
STO VAR1
CLA =O777777776
CIO 124
XOR =O777777776
TNZ L15P1N
* SAME AS ABOVE FOR CIO 130
L8P6 CLA H8P6
STO VAR1
CLA H9P1
H9P1 HPC L9P1
STO VAR2
CLA =O777777776
CIO 130
XOR =O777777776
TNZ L15P1N
L8P7 CLA LCR4 FOR PROGRAM COMPATIBILITY
TMI L8P9
CLA LCR3
TMI L8P9
CLA LCR5
TMI L8P9
L8P8 CLA K77 SET AND RESET ALL DO S
CIO 210
CLA ZERO
CIO 210
HOP H9P3
HOP H9P1
L8P9 TRA L20P2A DELAY
TRA L8P8
L15P1N TRA L95P1
DOG ,,375
KMR OCT 440000000
DOG ,1,375
KMP OCT 420000000
DOG ,2,375
KMC OCT 410000000
DOG ,3,375
KMD OCT 404000000
DOG ,4,375
KME OCT 402000000
DOG ,5,375
# PAGE 30, SEQUENCE 13640-13860
KMF OCT 401000000
DOG ,6,375
KMG OCT 400400000
DOG ,7,375
KMQ OCT 400001000
DOG ,10,375
KMB OCT 500000000
DOG ,11,375
KMH OCT 400200000
DOG ,12,375
KMJ OCT 400100000
DOG ,13,375
KMK OCT 400040000
DOG ,14,375
KML OCT 400020000
DOG ,15,375
KMM OCT 400010000
DOG ,16,375
KMN OCT 400004000
DOG ,17,375
KMO OCT 400002000
DOG 1,07,375
KMA OCT 200000000
# PAGE 31, SEQUENCE 13880-14440
DOG ,14,0
H9P2 HPC L9P2
H9P4 HPC L9P4
H9P5 HPC L9P5
H9P6 HPC L9P6
H9P7 HPC L9P7
H9P8 HPC L9P8
H9P9 HPC L9P9
H9P10 HPC L9P10
H9P11 HPC L9P11
H9P12 HPC L9P12
H9P13 HPC L9P13
H9P14 HPC L9P14
H9P15 HPC L9P15
H9P16 HPC L9P16
H9P17 HPC L9P17
H9P18 HPC L9P18
H9P19 HPC L9P19
H9P20 HPC L9P20
H9P21 HPC L9P21
H9P22 HPC L9P22
H9P23 HPC L9P23
H9P24 HPC L9P24
H9P25 HPC L9P25
DOG ,14,31
H9P26 HPC L9P26
H9P27 HPC L9P27
H9P28 HPC L9P28
H9P29 HPC L9P29
H9P30 HPC L9P30
H9P31 HPC L9P31
H9P32 HPC L9P32
H9P33 HPC L9P33
H9P34 HPC L9P34
H9P35 HPC L9P35
H9P36 HPC L9P36
H9P37 HPC L9P37
H9P38 HPC L9P38
H9P39 HPC L9P39
H9P40 HPC L9P40
H9P41 HPC L9P41
H9P42 HPC L9P42
H9P43 HPC L9P43
H9P44 HPC L9P44
H9P45 HPC L9P45
H9P46 HPC L9P46
H9P47 HPC L9P47
H9P48 HPC L9P48
H9P49 HPC L9P49
H9P50 HPC L9P50
H9P51 HPC L9P51
H9P52 HPC L9P52
H9P53 HPC L9P53
H9P54 HPC L9P54
H9P55 HPC L9P55
H9P56 HPC L9P56
H9P57 HPC L9P57
# PAGE 32, SEQUENCE 14450-15010
H9P58 HPC L9P58
H9P59 HPC L9P59
H9P60 HPC L9P60
H9P61 HPC L9P61
H9P62 HPC L9P62
H9P63 HPC L9P63
H9P64 HPC L9P64
H9P65 HPC L9P65
H9P66 HPC L9P66
H9P67 HPC L9P67
H9P68 HPC L9P68
H9P69 HPC L9P69
H9P70 HPC L9P70
H9P71 HPC L9P71
H9P72 HPC L9P72
* ROUTINE THREE
* TEST CIO CODES,ACCUMULATOR INTERFACE,DISCRETE
* OUTPUTS, DISCRETE INPUTS, INTERRUPTS
* FOR CIO SELF TEST B SWITCH NR 1 MUST BE ON
L9P1 CLA LCR3
TMI L9P2
TNZ L20P1A
TRA L2P1
L20P1A TRA L20P1
* INITIALIZE
L9P2 CLA H9P2
STO VAR4
CLA =O777777776
CIO 000
CLA ZERO
STO VAR5
TRA L9P3 RST INT LATCHES
TRA L9P4
L9P3 STO 776 SUBROUTINE TO RESET ALL INT LATCHES
CIO 010
CIO 014
CIO 020
CIO 024
CIO 030
CIO 034
CIO 040
CIO 044
CIO 050
CIO 054
CIO 060
CIO 064
CIO 070
CIO 074
CIO 100
CIO 104
HOP 776
* TEST INTERRUPT REGISTER FOR ZERO CONDITION
ORG ,2,,2,,14,
L9P4 CIO 154
TNZ L15P1P
* BEGIN TEST OF CIO CODES
# PAGE 33, SEQUENCE 15020-15580
L9P5 CLA H9P5
STO VAR4
CLA =O777777776
CIO 000
CIO 154 READ INT REG R
TNZ L15P1P
L9P6 CLA H9P6
STO VAR4
CIO 003
CIO 154
TNZ L15P1P
L9P7 CLA H9P7
STO VAR4
CLA ZERO
CIO 004
CIO 154
TNZ L15P1P
L9P8 CLA H9P8
STO VAR4
CIO 001 SET I3
CIO 154
XOR =O100000000
TNZ L15P1P
L9P9 CIO 020 RST I3
CLA H9P9
STO VAR4
CIO 002 SET I1
CIO 154
XOR =O400000000
TNZ L15P1P
L9P10 CIO 010 RST I1
CLA H9P10
STO VAR4
CIO 005 SET I4
CIO 154
XOR =O040000000
TNZ L15P1P
L9P11 CIO 024 RST I4
CLA H9P11
STO VAR4
CIO 006 SET I2
CIO 154
XOR =O200000000
TNZ L15P1P
L9P12 CIO 014 RST I2
CLA H9P12
STO VAR4
CIO 007
CIO 154
TNZ L15P1P
L9P13 CLA H9P13
STO VAR4
CIO 011 SET I5
CIO 154
XOR =O020000000
TNZ L15P1P
L9P14 CIO 030 RST I5
# PAGE 34, SEQUENCE 15590-16150
CLA H9P14
STO VAR4
CIO 012 SET I3
CIO 154
XOR =O100000000
TNZ L15P1P
L9P15 CIO 020 RST I3
CLA H9P15
STO VAR4
CIO 015 SET I6
CIO 154
XOR =O010000000
TNZ L15P1P
L9P16 CIO 034 RST I6
CLA H9P16
STO VAR4
CIO 016 SET I4
CIO 154
XOR =O040000000
TNZ L15P1P
L9P17 CIO 024 RST I4
CLA H9P17
STO VAR4
CIO 021 SET I7
CIO 154
XOR =O004000000
TNZ L15P1P
L9P18 CIO 040 RST I7
CLA H9P18
STO VAR4
CIO 022 SET I5
CIO 154
XOR =O020000000
TNZ L15P1P
L9P19 CIO 030 RST I5
CLA H9P19
STO VAR4
CIO 025 SET I8
CIO 154
XOR =O002000000
TNZ L15P1P
L9P20 CIO 044 RST I8
CLA H9P20
STO VAR4
CIO 026 SET I6
CIO 154
XOR =O010000000
TNZ L15P1P
L9P21 CIO 034 RST I6
CLA H9P21
STO VAR4
CIO 031 SET I9
CIO 154
XOR =O001000000
TNZ L15P1P
L9P22 CIO 050 RST I9
CLA H9P22
# PAGE 35, SEQUENCE 16160-16720
STO VAR4
CIO 032 SET I7
CIO 154
XOR =O004000000
TNZ L15P1P
L9P23 CIO 040 RST I7
CLA H9P23
STO VAR4
CIO 035 SET I10
CIO 154
XOR =O000400000
TNZ L15P1P
L9P24 CIO 054 RST I10
CLA H9P24
STO VAR4
CIO 036 SET I8
CIO 154
XOR =O002000000
TNZ L15P1P
L9P25 CIO 044 RST I8
CLA H9P25
STO VAR4
CIO 041 SET I11
CIO 154
XOR =O000200000
TNZ L15P1P
L9P26 CIO 060 RST I11
CLA H9P26
STO VAR4
CIO 042 SET I9
CIO 154
XOR =O001000000
TNZ L15P1P
L9P27 CIO 050 RST I9
CLA H9P27
STO VAR4
CIO 045 SET I12
CIO 154
XOR =O000100000
TNZ L15P1P
L9P28 CIO 064 RST I12
CLA H9P28
STO VAR4
CIO 046 SET I10
CIO 154
XOR =O000400000
TNZ L15P1P
L9P29 CIO 054 RST I10
CLA H9P29
STO VAR4
CIO 051 SET I13
CIO 154
XOR =O000040000
TNZ L15P1P
L9P30 CIO 070 RST 13
CLA H9P30
STO VAR4
# PAGE 36, SEQUENCE 16730-17290
CIO 052 SET 11
CIO 154
XOR =O000200000
TNZ L15P1P
L9P31 CIO 060 RST 11
CLA H9P31
STO VAR4
CIO 055 SET 14
CIO 154
XOR =O000020000
TNZ L15P1P
L9P32 CIO 074 RST 14
CLA H9P32
STO VAR4
CIO 056 SET 12
CIO 154
XOR =O000100000
TNZ L15P1P
L9P33 CIO 064 RST 12
CLA H9P33
STO VAR4
CIO 061 SET 15
CIO 154
XOR =O000010000
TNZ L15P1P
L9P34 CIO 100 RST 15
CLA H9P34
STO VAR4
CIO 062 SET 13
CIO 154
XOR =O000040000
TNZ L15P1P
L9P35 CIO 070 RST 13
CLA H9P35
STO VAR4
CIO 065 SET 9
CIO 154
XOR =O001000000
TNZ L15P1P
L9P36 CIO 050 RST 9
CLA H9P36
STO VAR4
CIO 066 SET 14
CIO 154
XOR =O000020000
TNZ L15P1P
L9P37 CIO 074 RST 14
CLA H9P37
STO VAR4
CIO 071 SET 10
CIO 154
XOR =O000400000
TNZ L15P1P
L9P38 CIO 054 RST 10
CLA H9P38
STO VAR4
CIO 072 SET 15
# PAGE 37, SEQUENCE 17300-17860
CIO 154
XOR =O000010000
TNZ L15P1P
L9P39 CIO 100 RST 15
CLA H9P39
STO VAR4
CIO 075 SET 1
CIO 154
XOR =O400000000
TNZ L15P1P
TRA L9P40
ORG ,2,1,2,,14,
L9P40 CIO 010 RST 1
CLA H9P40
STO VAR4
CIO 076 SET 11
CIO 154
XOR =O000200000
TNZ L15P1P
L9P41 CIO 060 RST 11
CLA H9P41
STO VAR4
CIO 101 SET 2
CIO 154
XOR =O200000000
TNZ L15P1P
L9P42 CIO 014 RST 2
CLA H9P42
STO VAR4
CIO 102 SET 13
CIO 154
XOR =O000040000
TNZ L15P1P
L9P43 CIO 070 RST 13
CLA H9P43
STO VAR4
CIO 105 SET 3
CIO 154
XOR =O100000000
TNZ L15P1P
L9P44 CIO 020 RST 3
CLA H9P44
STO VAR4
CIO 106 SET 1
CIO 154
XOR =O400000000
TNZ L15P1P
L9P45 CIO 010 RST 1
CLA H9P45
STO VAR4
CIO 111 SET 4
CIO 154
XOR =O040000000
TNZ L15P1P
L9P46 CIO 024 RST 4
CLA H9P46
STO VAR4
# PAGE 38, SEQUENCE 17870-18430
CIO 112 SET 2
CIO 154
XOR =O200000000
TNZ L15P1P
L9P47 CIO 014 RST 2
CLA H9P47
STO VAR4
CIO 115 SET 5
CIO 154
XOR =O020000000
TNZ L15P1P
L9P48 CIO 030 RST 5
CLA H9P48
STO VAR4
CIO 116 SET 3
CIO 154
XOR =O100000000
TNZ L15P1P
L9P49 CIO 020 RST 3
CLA H9P49
STO VAR4
CIO 121 SET 6
CIO 154
XOR =O010000000
TNZ L15P1P
L9P50 CIO 034 RST 6
CLA H9P50
STO VAR4
CIO 122 SET 4
CIO 154
XOR =O040000000
TNZ L15P1P
L9P51 CIO 024 RST 4
CLA H9P51
STO VAR4
CIO 125 SET 7
CIO 154
XOR =O004000000
TNZ L15P1P
L9P52 CIO 040 RST 7
CLA H9P52
STO VAR4
CIO 126 SET 5
CIO 154
XOR =O020000000
TNZ L15P1P
L9P53 CIO 030 RST 5
CLA H9P53
STO VAR4
CIO 131 SET 8
CIO 154
XOR =O002000000
TNZ L15P1P
L9P54 CIO 044 RST 8
CLA H9P54
STO VAR4
CIO 132 SET 6
# PAGE 39, SEQUENCE 18440-19000
CIO 154
XOR =O010000000
TNZ L15P1P
L9P55 CIO 034 RST 6
CLA H9P55
STO VAR4
CIO 135 SET 9
CIO 154
XOR =O001000000
TNZ L15P1P
L9P56 CIO 050 RST 9
CLA H9P56
STO VAR4
CIO 136 SET 7
CIO 154
XOR =O004000000
TNZ L15P1P
L9P57 CIO 040 RST 7
CLA H9P57
STO VAR4
CIO 141 SET 10
CIO 154
XOR =O000400000
TNZ L15P1P
L9P58 CIO 054 RST10
CLA H9P58
STO VAR4
CIO 142 SET 8
CIO 154
XOR =O002000000
TNZ L15P1P
L9P59 CIO 044 RST 8
CLA H9P59
STO VAR4
CIO 145 SET 11
CIO 154
XOR =O000200000
TNZ L15P1P
L9P60 CIO 060 RST 11
CLA H9P60
STO VAR4
CIO 146 SET 9
CIO 154
XOR =O001000000
TNZ L15P1P
L9P61 CIO 050 RST 9
CLA H9P61
STO VAR4
CIO 151 SET 12
CIO 154
XOR =O000100000
TNZ L15P1P
L9P62 CIO 064 RST 12
CLA H9P62
STO VAR4
CIO 152 SET 10
CIO 154
# PAGE 40, SEQUENCE 19010-19570
XOR =O000400000
TNZ L15P1P
L9P63 CIO 054 RST 10
CLA H9P63
STO VAR4
CIO 156 SET 11
CIO 154
XOR =O000200000
TNZ L15P1P
L9P64 CIO 060 RST 11
CLA H9P64
STO VAR4
CIO 162 SET 12
CIO 154
XOR =O000100000
TNZ L15P1P
L9P65 CIO 064 RST 12
CLA H9P65
STO VAR4
CIO 166 SET 13
CIO 154
XOR =O000040000
TNZ L15P1P
L9P66 CIO 070 RST 13
CLA H9P66
STO VAR4
CIO 172 SET 14
CIO 154
XOR =O000020000
TNZ L15P1P
L9P67 CIO 074 RST 14
CLA H9P67
STO VAR4
CIO 176 SET 15
CIO 154
XOR =O000010000
TNZ L15P1P
L9P68 CIO 100 RST 15
CLA H9P68
STO VAR4
CIO 202 SET 12
CIO 154
XOR =O000100000
TNZ L15P1P
L9P69 CIO 064 RST 12
CLA H9P69
STO VAR4
CIO 206 SET 14
CIO 154
XOR =O000020000
TNZ L15P1P
L9P70 CIO 074 RST 14
CLA H9P70
STO VAR4
CIO 212 SET 1
CIO 154
XOR =O400000000
# PAGE 41, SEQUENCE 19580-19880
TNZ L15P1P
L9P71 CIO 010 RST 1
CLA H9P71
STO VAR4
CIO 216 SET 2
CIO 154
XOR =O200000000
TNZ L15P1P
L9P72 CIO 014 RST 2
CLA H9P72
STO VAR4
CIO 155 TEST SPARES
CIO 161
CIO 165
CIO 171
CIO 175
TNZ L15P1P
CIO 154
TNZ L15P1P
TRA L10P1
L15P1P STO 777
LPPA STO TEMP
CLA 777
STO VAR2
CLA VAR4
STO VAR1
CLA ZERO
STO VAR4
HOP H9P3
CLA TEMP
HOP H95P1
# PAGE 42, SEQUENCE 19900-20460
* BEGIN TEST OF CIO CODES GROUP 1
ORG ,3,,31,,14,
L10P1 CDS 0,14
CLA H10P1
STO VAR4
CIO 002 004 CAUSE HOP 400
CIO 006
CIO 012 010 RST1,014 RST 2
CIO 016
CIO 022 020 RST 3, 024 RST 4
CIO 026
CIO 032 030 RST5, 034 RST6
CIO 036
CIO 042 040 RST 7, 044 RST 8
CIO 046
CIO 052 050 RST9, 054 RST 10
CIO 056
CIO 062 060 RST 11, 064 RST 12
CIO 066
CIO 072 070 RST 13, 074 RST 14
CIO 000 100 RST 15
CIO 154 READ INT REG
XOR =O777770000
TNZ L15P1Q
CIO 010 RST 1, 014 RST 2, 020 RST 3
CIO 154 030 RST 5, 040 RST 7
XOR =O377770000 050 RST 9, 060 RST 11
TNZ L15P1Q 070 RST 13, 110 CAUSES HOP
L10P2 CLA H10P2
STO VAR4
CLA ZERO
CIO 014 RST 2, 114 SETS CST AND STOPS PROG.
TNZ L15P1Q 214 READS A SWTS, 314 SP
L10P3 CLA H10P3
STO VAR4
CIO 154
XOR =O177770000 024,034,044,054,064,074
TNZ L15P1Q RESET 4,6,8,10,12,14
L10P4 CLA H10P4
STO VAR4
CIO 002 SET 1
CLA =O470000000
CIO 020 RST 3
XOR =O470000000
TNZ L15P1Q 220 READS B SWT 1
CIO 154
XOR =O477770000 0010 RST 1, 120 SET 3
TNZ L15P1Q 320 SP
L10P5 CLA H10P5
STO VAR4
CLA =O110000000
CIO 024 RST 4
CIO 154 123 SET 3,7,8, 224 SET 3,6
XOR =O437770000 324 SP
TNZ L15P1Q
L10P6 CLA H10P6
STO VAR4
# PAGE 43, SEQUENCE 20470-21030
CLA =O010000000
CIO 030 RST 5, 130 SET 3 THRU 9
CIO 154 230 SP
XOR =O417770000
TNZ L15P1Q
L10P7 CLA H10P7
STO VAR4
CLA ZERO
CIO 034 RST 6 , 234 SP
CIO 154
XOR =O407770000
TNZ L15P1Q
L10P8 CLA H10P8
STO VAR4
CLA ZERO
CIO 040 RST 7
CIO 154 140 PLT X, 240 SP
XOR =O403770000
TNZ L15P1Q
L10P9 CLA H10P9
STO VAR4
CLA ZERO
CIO 044 RST 8
CIO 154 144 PLT Y, 244 SP
XOR =O401770000
TNZ L15P1Q
L10P10 CLA H10P10
STO VAR4
CLA ZERO
CIO 050 RST 9
CIO 154 150 PLT Z, 250 SP
XOR =O400770000
TNZ L15P1Q
L10P11 CLA H10P11
STO VAR4
CLA ZERO
CIO 054 RST 10
TNZ L15P1Q 154 READ INT REG., 254 SP
L10P12 CLA H10P12
STO VAR4
CIO 154
XOR =O400370000
TNZ L15P1Q
L10P13 CLA H10P13
STO VAR4
CLA =O100000000
CIO 060 RST 11
CIO 154 160 SET 3,8,12
XOR =O400170000 260 SP
TNZ L15P1Q
L10P14 CLA H10P14
STO VAR4
CIO 064 RST 12
CIO 154 164 PRT OCTAL
XOR =O400070000 264 SP
TNZ L15P1Q
L10P15 CLA H10P15
# PAGE 44, SEQUENCE 21040-21600
STO VAR4
CIO 070 RST 13
CIO 154 170 PRT BCD
XOR =O400030000 270 SP
TNZ L15P1Q
L10P16 CLA H10P16
STO VAR4
CIO 074 174,274 SP
CIO 154
XOR =O400010000
TNZ L15P1Q
L10P17 CLA H10P17
STO VAR4
CIO 100 RST 15
CIO 154 200,300 SP
XOR =O400000000
TNZ L15P1Q
* TEST DISCCRETE OUTPUTS + INPUTS ALL ZERO
L10P18 CLA H10P18
STO VAR4
CLA ZERO
CIO 210 RESET DO S
TNZ L15P1Q 214,220 READ A,B SWTS
CLA =O000000006
CIO 214 READ A SWTS
AND =O000001760 17-22 DO S + DI S ALL DOWN
TNZ L15P1Q
* CIO CODES 104 THRU 220
L10P19 CLA H10P19
STO VAR4
CLA =O660000176
CIO 110 010 RST1, 210 SET D.O.
CIO 154 114 STOP PRG, 120 SET 5
XOR =O400000000 130 SET 5,7,8
TNZ L15P1Q
L10P20 CLA H10P20
STO VAR4
CIO 006 SET 2
CLA =O300000040
CIO 214 CHECK FOR D.O. SET
AND =O000001760
TNZ L15P1Q
CIO 154 224 ACC SET 3
XOR =O600000000 204 TURN ON P20 LIGHT
TNZ L15P1Q 014 RST 2
L10P21 CLA H10P21
STO VAR4
CIO 072 SET 15
CLA =O120000000
CIO 104 124 SET 6,7,8
CIO 154 100 RST 15,004 FORCED HOP
XOR =O600010000 304 SP
TNZ L15P1Q
CLA LCR4 IS ROUTINE 4 SELECTED
TMI L10P22
CIO 010
CIO 014
# PAGE 45, SEQUENCE 21610-22170
CIO 100
TRA L10P27
L10P22 CLA H10P22
STO VAR4
CIO 012 SET3
CLA =O460000000
CIO 120 SET 5,7,9
CLA LCR2
TMI *+2
TRA *+2
TRA L20P2A
CLA =O000000004
CIO 210
CLA ZERO
CIO 210
CIO 154 123 SET 3,7,8,130 SET 3 THRU 9
AND =O177770000 020 RST 3,100 RST 15,320 SP
XOR =O125010000
* CIO 120,124,130 MAY SET 1 OR 2 IF CASE SHIFT OCCURS
TNZ L15P1Q
L10P23 CLA H10P23
STO VAR4
CIO 010 RESET 1,3,5,7,9,15
CIO 020
CIO 030
CIO 040
CIO 050
CIO 100
CIO 016 SET 4
CLA =O510000000
CIO 124 SET 6,7,8
XOR =O510000000 154 READ INT REG
TNZ L15P1Q
L10P24 CLA H10P24 024 RST 4,120 SET 3,7,9
STO VAR4 224 SET 1,3,6,134 SET 8,10,12
CLA =O000000004
CIO 210
CLA ZERO
CIO 210
CIO 154 144 PLT,164 PRT OCTAL
AND =O177770000 174,324 SP
XOR =O056000000
TNZ L15P1Q
TRA L10P25
ORG ,3,1,2,,14,
L10P25 CLA H10P25
STO VAR4
CIO 020 RST 3,4,7,8
CIO 024
CIO 040
CIO 044
CIO 022 SET 5
CLA =O300000000
CIO 130 SET 4,5,6,7,8
CLA =O000000004
CIO 210
CLA ZERO
# PAGE 46, SEQUENCE 22180-22740
CIO 210
CIO 154 030 RST 5,134 SET 7,12
AND =O177770000 120 SET 3,6,8,160 SET 3,8,12
XOR =O076000000 110 HOP, 170 PRT BCD
TNZ L15P1Q 230 SP
L10P26 CLA H10P26
STO VAR4
CIO 010 RST 1 THRU 5,7,8
CIO 014
CIO 020
CIO 024
CIO 030
CIO 040
CIO 044
CLA =O060000000
CIO 134 SET 11,14
CLA =O000000004
CIO 210
CLA ZERO
CIO 210
CIO 154 034 RST 6,124 SET 5,7,8
XOR =O010220000 130 SET 5,7,8,164 PRT OCTAL
TNZ L15P1Q
L10P27 CLA H10P27
STO VAR4
CIO 034
CIO 060
CIO 074
CIO 032 SET 7
CIO 036 SET 8
CIO 042 SET 9
CLA ZERO
CIO 140 040 RST 7
CIO 144 044 RST 8
CIO 154
XOR =O007000000
TNZ L15P1Q
L10P28 CLA H10P28
STO VAR4
CLA ZERO
CIO 150
TNZ L15P1Q 154 READ INT REG
CIO 154
XOR =O007000000 050 RST 9
TNZ L15P1Q
L10P29 CLA H10P29
STO VAR4
CIO 052 SET 11
CLA LCR5 IS ROUTINE 5 SELECTED
TMI *+4
CLA =O1321 SET 3,5,6,8,12
CIO 224
TRA L10P30
CLA =O130000000
CIO 160 SET 3,5,6,8,12
CLA =O000000176 RESET DATA LINES
CIO 210
# PAGE 47, SEQUENCE 22750-23310
CLA ZERO
CIO 210
CIO 154
XOR =O137300000 060 RST 11,164 PRT OCTAL
TNZ L15P1Q 260 SP
L10P30 CLA H10P30
STO VAR4
CLA =O040000000
CIO 164 160 SET 4
CIO 154 064 RST 12
XOR =O137300000
TNZ L15P1Q
L10P31 CLA H10P31
STO VAR4
CIO 062 SET 13
CIO 170 070 RST 13
CIO 154
XOR =O137340000
TNZ L15P1Q
L10P33 CLA H10P33
STO VAR4
CIO 066 SET 14
CIO 072 SET 15
CLA ZERO
CIO 174 074 RST 14
CLA =O000000006
CIO 200 204 RST P LIGHTS TO 3
CIO 154 210 SET D.O. 1 + 2
XOR =O137370000 100 RST 15
TNZ L15P1Q
L10P34 CLA H10P34
STO VAR4
CLA ZERO
CIO 214
AND =O000001760 CHECK FOR DO 5+6
TNZ L15P1Q
L10P35 CLA H10P35
STO VAR4
CLA ZERO
CIO 204 214 READ A SWTS
TNZ L15P1Q
L10P36 CLA H10P36
STO VAR4
CLA =O400000000
CIO 220 224 SET 1
XOR =O200000000
TNZ L15P1Q
L10P37 CLA H10P37
STO VAR4
CIO 154
XOR =O137370000
TNZ L15P1Q
L10P38 CLA H10P38
STO VAR4
CIO 020 RESET INT REG
CIO 030
CIO 034
# PAGE 48, SEQUENCE 23320-23880
CIO 040
CIO 044
CIO 050
CIO 060
CIO 064
CIO 070
CIO 074
CIO 100
CLA =O000000176
PIO 210 CIO 210 SETS D.O.S
CIO 214
AND =O000001760
TNZ L15P1Q
* TEST DESCRETE INPUTS AND OUTPUTS
L10P39 CLA H10P39
STO VAR4
CLA =O000000002
CIO 210 SET DO 1
* CAL POINT NR 1
CIO 214
AND =O000001760
XOR =O000000020
TNZ L15P1Q TEST DO 1, DI 1, CIO 210 UP
L10P40 CLA H10P40
STO VAR4
CLA =O000000004
CIO 210 RST DO1, SET DO 2
* CAL POINT NR 2
CIO 214
AND =O000001760
XOR =O000000040 TEST DO2, DI2 UP
TNZ L15P1Q
L10P41 CLA H10P41
STO VAR4
CLA =O000000010
CIO 210 RST DO2, SET DO3
* CAL POINT NR 3
CIO 214
AND =O000001760
XOR =O000000100 TEST DO 3, DI 3 UP
TNZ L15P1Q
L10P42 CLA H10P42
STO VAR4
CLA =O000000020
CIO 210 RST DO 3, SET DO 4
* CAL POINT NR 4
CIO 214
AND =O000001760
XOR =O000000200 TEST DO 4, DI 4 UP
TNZ L15P1Q
L10P43 CLA H10P43
STO VAR4
CLA =O000000040
CIO 210 RST DO 4, SET DO 5
* CAL POINT NR 5
CIO 214
AND =O000001760
# PAGE 49, SEQUENCE 23890-24450
XOR =O000000400 TEST DO 5, DI 5 UP
TNZ L15P1Q
L10P44 CLA H10P44
STO VAR4
CLA =O000000100
CIO 210 RST DO 5, SET DO 6
* CAL POINT NR 6
CIO 214
AND =O000001760
XOR =O000001000 TEST DO 6, DI 6 UP
TNZ L15P1Q
L10P45 CLA H10P45
STO VAR4
CLA ZERO
CIO 210 RST DO 6
CIO 214
AND =O000001760 TEST RST DO 6
TNZ L15P1Q
TRA L11P1
L15P1Q STO TEMP
CLA H11P1
STO VAR2
CLA H10P1
STO VAR1
HOP H9P3
CLA TEMP
TRA L95P1
# This following line was not in the original source code,
# and is a workaround for what I believe is a bug in the
# original assembler that I haven't yet figured out how to
# reproduce in the modern assembler.
DOG 0,14,113 # workaround
H10P1 HPC L10P1
H10P2 HPC L10P2
H10P3 HPC L10P3
H10P4 HPC L10P4
H10P5 HPC L10P5
H10P6 HPC L10P6
H10P7 HPC L10P7
H10P8 HPC L10P8
H10P9 HPC L10P9
H10P10 HPC L10P10
H10P11 HPC L10P11
H10P12 HPC L10P12
H10P13 HPC L10P13
H10P14 HPC L10P14
H10P15 HPC L10P15
H10P16 HPC L10P16
H10P17 HPC L10P17
H10P18 HPC L10P18
H10P19 HPC L10P19
H10P20 HPC L10P20
H10P21 HPC L10P21
H10P22 HPC L10P22
H10P23 HPC L10P23
H10P24 HPC L10P24
H10P25 HPC L10P25
H10P26 HPC L10P26
H10P27 HPC L10P27
H10P28 HPC L10P28
H10P29 HPC L10P29
H10P30 HPC L10P30
# PAGE 50, SEQUENCE 24460-24590
H10P31 HPC L10P31
H10P33 HPC L10P33
H10P34 HPC L10P34
H10P35 HPC L10P35
H10P36 HPC L10P36
H10P37 HPC L10P37
H10P38 HPC L10P38
H10P39 HPC L10P39
H10P40 HPC L10P40
H10P41 HPC L10P41
H10P42 HPC L10P42
H10P43 HPC L10P43
H10P44 HPC L10P44
H10P45 HPC L10P45
# PAGE 51, SEQUENCE 24610-25060
* TEST ACCUMULATOR INTERFACE
L11P1 CLA H11P1
STO VAR4
HOP H9P3
CLA ZERO
CIO 224 220 READ B SWT = 1
TNZ L15P1R
L11P2 CLA H11P2
STO VAR4
CIO 154
TNZ L15P1R CHECK FOR ALL INTERFACE UP
L11P3 CLA H11P3
STO VAR4
CLA =O400000002 AS, A25
CIO 224
CIO 154
XOR =O400200000
TNZ L15P1R
L11P4 CLA H11P4
STO VAR4
CIO 010 RST 1
CIO 060 RST 11
CLA =O200000004 A1,A24
CIO 224
CIO 154
XOR =O200400000
TNZ L15P1R
L11P5 CLA H11P5
STO VAR4
CIO 014 RST 2
CIO 054 RST 10
CLA =O100000010 A2,A23
CIO 224
CIO 154
XOR =O101000000
TNZ L15P1R
TRA L11P6
L15P1R STO 777
LPRA STO TEMP
CLA VAR4
STO VAR1
CLA 777
STO VAR2
HOP H9P3
CLA TEMP
HOP H95P1
# PAGE 52, SEQUENCE 25080-25640
ORG ,4,,2,,14,
L11P6 CLA H11P6
STO VAR4
CIO 020 RST3
CIO 050 RST9
CLA =O040000020 A3,A22
CIO 224
CIO 154
XOR =O042000000
TNZ LPR
L11P7 CLA H11P7
STO VAR4
CIO 024 RST 4
CIO 044 RST 8
CLA =O020000040 A4, A21
CIO 224
CIO 154
XOR =O024000000
TNZ LPR
L11P8 CLA H11P8
STO VAR4
CIO 030 RST 5
CIO 040 RST 7
CLA =O010100000 A5, A11
CIO 224
CIO 154
XOR =O010100000
TNZ LPR
L11P9 CLA H11P9
STO VAR4
CIO 034 RST 6
CIO 064 RST 12
CLA =O004040000 A6, A12
CIO 224
CIO 154
XOR =O004040000
TNZ LPR
TRA L11P10
ORG ,4,,53,,14,
L11P10 CLA H11P10
STO VAR4
CIO 040 RST 7
CIO 070 RST 13
CLA =O002020100 A7, A13, A20
CIO 224
CIO 154
XOR =O012020000
TNZ LPR
L11P11 CLA H11P11
STO VAR4
CIO 044 RST 8
CIO 074 RST 14
CIO 034 RST 6
CLA =O001010200 A8, A14, A19
CIO 224
CIO 154
XOR =O021010000
# PAGE 53, SEQUENCE 25650-26210
TNZ LPR
L11P12 CLA H11P12
STO VAR4
CIO 030 RST 5
CIO 050 RST 9
CIO 100 RST 15
CLA =O000404400 A9, A15, A18
CIO 224
CIO 154
XOR =O440400000
TNZ LPR
L11P13 CLA H11P13
STO VAR4
CIO 010 RST 1
CIO 024 RST 4
CIO 054 RST 10
CLA =O000201000 A10, A17
CIO 224
CIO 154
XOR =O100200000
TNZ LPR
L11P14 CLA H11P14
STO VAR4
L11PA CIO 020 RST 3
CIO 060 RST 11
CLA =O000002000 A16
CIO 224
CIO 154
XOR =O200000000
TNZ LPR
L11P15 CLA H11P15
STO VAR4
CIO 014 RST 2
TRA L11P18
LPR STO 777
TRA LPRA
* CHECK PIO + A1 THRU A9 INTERFACE LINES
L11P18 CLA H11P18
STO VAR4
PIO 000
CIO 154
TNZ L11P28
L11P19 CLA H11P19
STO VAR4
PIO 001 SET INT 1
CIO 154
XOR =O400000000
TNZ L11P28
L11P20 CLA H11P20
STO VAR4
CIO 010 RST 1
PIO 002 SET 2
CIO 154
XOR =O200000000
TNZ L11P28
L11P21 CLA H11P21
# PAGE 54, SEQUENCE 26220-26780
STO VAR4
CIO 014 RST 2
PIO 004 SET 3
CIO 154
XOR =O100000000
TNZ L11P28
L11P22 CLA H11P22
STO VAR4
CIO 020 RST 3
PIO 010 SET 4
CIO 154
XOR =O040000000
TNZ L11P28
L11P23 CLA H11P23
STO VAR4
CIO 024 RST 4
PIO 020 SET 5
CIO 154
XOR =O020000000
TNZ L11P28
L11P24 CLA H11P24
STO VAR4
CIO 030 RST 5
PIO 040 SET 6
CIO 154
XOR =O010000000
TNZ L11P28
L11P25 CLA H11P25
STO VAR4
CIO 034 RST 6
PIO 100 SET 7
CIO 154
XOR =O004000000
TNZ L11P28
L11P26 CLA H11P26
STO VAR4
CIO 040 RST 4
PIO 200 SET 8
CIO 154
XOR =O002000000
TNZ L11P28
L11P27 CLA H11P27
STO VAR4
CIO 044 RST 8
PIO 400 SET 9
CIO 154
XOR =O001000000
TNZ L11P28
CIO 050 RST 9
* CHECK SERIAL DATA LINES AI3 + CIO DATA
L11P29 STO 776
CLA ZERO
STO VAR4
CLA =O252525252
CIO 234
CIO 001
XOR =O525252524
# PAGE 55, SEQUENCE 26790-27350
TNZ L11P33
L11P30 STO 776
CLA =O525252524
CIO 234
CIO 001
XOR =O252525250
TNZ L11P33
* CHECK PTRS + PIO DATA LINES
L11P31 STO 776
CLA =O252525252
STO 403
CLA ZERO
CIO 230
PIO 403
XOR =O525252524
# TNZ L11P33
TNZ *+1 # FIX_EMULATOR
L11P32 STO 776
CLA =O525252524
STO 403
CLA ZERO
CIO 230
PIO 403
XOR =O252525250
# TNZ L11P33
TNZ *+1 # FIX_EMULATOR
HOP H9P3
TRA L12P1
L11P28 STO 777
TRA LPPA
L11P33 STO 777
STO TEMP
CLA 777
STO VAR2
CLA 776
STO VAR1
HOP H9P3
CLA TEMP
HOP H95P1
# This following line was not in the original source code,
# and is a workaround for what I believe is a bug in the
# original assembler that I haven't yet figured out how to
# reproduce in the modern assembler.
DOG 0,14,170 # workaround
H11P1 HPC L11P1
H11P2 HPC L11P2
H11P3 HPC L11P3
H11P4 HPC L11P4
H11P5 HPC L11P5
H11P6 HPC L11P6
H11P7 HPC L11P7
H11P8 HPC L11P8
H11P9 HPC L11P9
H11P10 HPC L11P10
H11P11 HPC L11P11
H11P12 HPC L11P12
H11P13 HPC L11P13
H11P14 HPC L11P14
H11P15 HPC L11P15
H11P18 HPC L11P18
H11P19 HPC L11P19
H11P20 HPC L11P20
H11P21 HPC L11P21
# PAGE 56, SEQUENCE 27360-27410
H11P22 HPC L11P22
H11P23 HPC L11P23
H11P24 HPC L11P24
H11P25 HPC L11P25
H11P26 HPC L11P26
H11P27 HPC L11P27
# PAGE 57, SEQUENCE 27430-27990
* TEST PIO INTERRUPTS
ORG ,6,,1,,15,0
H12P3 HPC L12P3
H12P5 HPC L12P5
H13P1 HPC L13P1
H13P3 HPC L13P3
H13P5 HPC L13P5
H14P1 HPC L14P1
H14P3 HPC L14P3
H14P5 HPC L14P5
H15P1 HPC L15P1
H15P3 HPC L15P3
H15P5 HPC L15P5
H16P1 HPC L16P1
H16P3 HPC L16P3
H16P5 HPC L16P5
H17P1 HPC L17P1
H12P1 HPC L12P1
H12P2 HPC L12P2
H12P4 HPC L12P4
H12P6 HPC L12P6
H13P2 HPC L13P2
H13P4 HPC L13P4
H13P6 HPC L13P6
H14P2 HPC L14P2
H14P4 HPC L14P4
H14P6 HPC L14P6
H15P2 HPC L15P2
H15P4 HPC L15P4
H15P6 HPC L15P6
H16P2 HPC L16P2
H16P4 HPC L16P4
H16P6 HPC L16P6
L12P1 CLA H12P1
STO VAR4
CLA H12P2
STO 400
CLA H12P4
STO 401
CLA H12P6
STO 402
CLA H13P2
STO 403
CLA H13P4
STO 404
CLA H13P6
STO 405
CLA H14P2
STO 406
CLA H14P4
STO 407
CLA H14P6
STO 410
CLA H15P2
STO 411
CLA H15P4
# PAGE 58, SEQUENCE 28000-28560
STO 412
CLA H15P6
STO 413
CLA H16P2
STO 414
CLA H16P4
STO 415
CLA H16P6
STO 416
CLA =O777777776
CIO 224 SET ALL INT LATCHES
* CAL POINT NR 7
CIO 110 RST MAIN PTC INT LATCH
* CAL POINT NR 8
CLA =O000000002 REMOVE INH ON INT 1
CIO 004
* SHOULD FORCE HOP 400 TO L12P2
L12P3 STO 777 SAVE PREVIOUS LOCN+1
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O200000000
TNZ L15P1S
CLA H12P3
STO VAR4
CLA =O777777776
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000000004 REMOVE INH ON INT 2
CIO 004
* SHOULD FORCE HOP 401 TO L12P4
L12P5 STO 777
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O100000000
TNZ L15P1S
CLA H12P5
STO VAR4
CLA =O777777776
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000000010 REMOVE INH ON INT 3
CIO 004
* SHOULD FORCE HOP 402 TO L12P6
L13P1 STO 777
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O040000000
TNZ L15P1S
CLA H13P1
STO VAR4
CLA =O777777776
# PAGE 59, SEQUENCE 28570-29130
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000000020 REMOVE INH ON INT 4
CIO 004
* SHOULD FORCE HOP 403 TO L13P2
L13P3 STO 777
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O020000000
TNZ L15P1S
CLA H13P3
STO VAR4
CLA =O777777776
CIO 000 SET INT HINHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000000040 REMOVE INH ON INT 5
CIO 004
* SHOULD FORCE HOP 404 TO L13P4
L13P5 STO 777
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O010000000
TNZ L15P1S
CLA H13P5
STO VAR4
CLA =O777777776
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000000100 REMOVE INH ON INT 6
CIO 004
* SHOULD FORCE HOP 405 TO L13P6
L14P1 STO 777
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O004000000
TNZ L15P1S
CLA H14P1
STO VAR4
CLA =O777777776
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000000200 REMOVE INH ON INT 7
CIO 004
* SHOULD FORCE HOP 406 TO L14P2
L14P3 STO 777
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O002000000
TNZ L15P1S
# PAGE 60, SEQUENCE 29140-29700
CLA H14P3
STO VAR4
CLA =O777777776
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000000400 REMOVE INH ON INT 8
CIO 004
* SHOULD FORCE HOP 407 TO L14P4
L14P5 STO 777
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O001000000
TNZ L15P1S
CLA H14P5
STO VAR4
CLA =O777777776
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000001000 REMOVE INH ON INT 9
CIO 004
* SHOULD FORCE HOP 410 TO L14P6
L15P1 STO 777
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O000400000
TNZ L15P1S
CLA H15P1
STO VAR4
CLA =O777777776
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000002000 REMOVE INH ON INT10
CIO 004
* SHOULD FORCE HOP 411 TO L15P2
L15P3 STO 777
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O000200000
TNZ L15P1S
CLA H15P3
STO VAR4
CLA =O777777776
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000004000 REMOVE INH ON INT 11
CIO 004
* SHOULD FORCE HOP 412 TO L15P4
L15P5 STO 777
STO TEMP
CLA 777
STO VAR5
# PAGE 61, SEQUENCE 29710-30270
CLA TEMP
XOR =O000100000
TNZ L15P1S
CLA H15P5
STO VAR4
CLA =O777777776
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000010000 REMOVE INH ON INT 12
CIO 004
* SHOULD FORCE HOP 413 TO L15P6
L16P1 STO 777
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O000040000
TNZ L15P1S
CLA H16P1
STO VAR4
CLA =O777777776
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000020000 REMOVE INH ON INT 13
CIO 004
* SHOULD FORCE HOP 414 TO L16P2
L16P3 STO 777
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O000020000
TNZ L15P1S
CLA H16P3
STO VAR4
CLA =O777777776
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000040000 REMOVE INH ON INT 14
CIO 004
* SHOULD FORCE HOP 415 TO L16P4
L16P5 STO 777
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O000010000
TNZ L15P1S
CLA H16P5
STO VAR4
CLA =O777777776
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
CLA =O000100000 REMOVE INH ON INT 15
CIO 004
* SHOULD FORCE HOP 416 TO L16P6
L17P1 STO 777
# PAGE 62, SEQUENCE 30280-30840
STO TEMP
CLA 777
STO VAR5
CLA TEMP
XOR =O000004000
TNZ L15P1S
CLA =O777777776
CIO 000 SET INT INHIBIT
CIO 110 RST MAIN INT LATCH
TRA L9P3 TO RESET INT REG
TRA L20P1
L12P2 CLA =O200000000
* CAL POINT NR 9
TRA L12P3
L12P4 CLA =O100000000
* CAL POINT NR 10
TRA L12P5
ORG ,6,1,0,,15,
* CAL POINT N4 11
L12P6 STO 777
CLA H12P6
STO VAR4
CLA 777
XOR H13P1
TNZ L15P1S
CLA =O040000000
TRA L13P1
L13P2 CLA =O020000000
* CAL POINT NR 12
TRA L13P3
L13P4 CLA =O010000000
* CAL POINT NR 13
TRA L13P5
L13P6 CLA =O004000000
* CAL POINT NR 14
TRA L14P1
L14P2 CLA =O002000000
* CAL POINT NR 15
TRA L14P3
L14P4 CLA =O001000000
* CAL POINT NR 16
TRA L14P5
L14P6 CLA =O000400000
* CAL POINT NR 17
TRA L15P1
L15P2 CLA =O000200000
* CAL POINT NR 18
TRA L15P3
L15P4 CLA =O000100000
* CAL POINT NR 19
TRA L15P5
L15P6 CLA =O000040000
* CAL POINT NR 20
TRA L16P1
L16P2 CLA =O000020000
* CAL POINT NR 21
TRA L16P3
# PAGE 63, SEQUENCE 30850-31390
L16P4 CLA =O000010000
* CAL POINT NR 22
TRA L16P5
L16P6 CLA =O000004000
* CAL POINT NR 23
TRA L17P1
L15P1S STO 777
STO TEMP
CLA 777
STO VAR2
CLA H12P1
STO VAR1
CLA TEMP
HOP H95P1
* TEST FOR PROPER OPERATION OF MANUAL INTERRUPT 16
* PRESS MANUAL INTERRUPT
* CLEAR AND ADD INTIND LOCATION AND INSPECT FOR BIT 16
ORG ,13,,310,,13,250
L17P2 STO 777
STO SAVE
CLA =O000002000
* CAL POINT NR 24
STO INTIND
CIO 220 READ B SWITCHES
STO TEMP2
AND =O020000000 B4
TNZ L17P3
L17P3A CIO 104
CIO 110
CLA SAVE
HOP 777
* TO EXECUTE SELECTED CIO ON COMMAND
L17P3 CLA K17P3B RESTORE CLA ADDRESS
AND KX7
STO TEMP3
CLA L17P3B
AND KX8
XOR TEMP3
STO L17P3B
CLA TEMP2
SHR 1
AND KX7
STO TEMP3 CIO ADDRESS
CLA L17P3C
AND KX8 REMOVE OLD ADDRESS
XOR TEMP3
STO L17P3C
CLA TEMP2
AND =O000000076
SHL 5
ADD L17P3B
STO L17P3B
L17P3B CLA BIT
L17P3C CIO 000
# PAGE 64, SEQUENCE 31400-31680
TRA L17P3A
K17P3B CLA BIT
BIT OCT 0
OCT 4
OCT 2
OCT 1
OCT 04
OCT 02
OCT 01
OCT 004
OCT 002
OCT 001
OCT 0004
OCT 0002
OCT 0001
OCT 00004
OCT 00002
OCT 00001
OCT 000004
OCT 000002
OCT 000001
OCT 0000004
OCT 0000002
OCT 0000001
OCT 00000004
OCT 00000002
OCT 00000001
OCT 000000004
OCT 000000002
# PAGE 65, SEQUENCE 31700-32260
* BEGINNING OF ROUTINE FOUR
* CHECK TYPEWRITER LOGIC AND INTERFACE
ORG ,6,1,60,,15,
L20P1 CLA LCR4
TMI L20P2
TNZ L29P1A
TRA L2P1
L29P1A TRA L29P1
L20P2 CDS 0,12
CLA H20P2
STO VAR4
CLA H20P3
STO VAR1
TRA L28P3 RESTORE INSTRUCTIONS
CLA K77
CIO 000 INHIBIT ALL INT
CLA ZERO
CIO 130 SET LOWER CASE
STO CTR
CLA =O000000132 EQUAL 45 DECIMAL
STO STOP
TRA L20P2A
TRA L20P3
ORG ,7,1,,,12,0
L20P2A STO 776 DELAY 87.6 MSEC.
CLA =O000002040
L20P2B SUB =O000000002
TNZ L20P2B
HOP 776
L20P3 CLA =O000000004 SET DO 2
CIO 210
CLA ZERO RESET D.O.2
CIO 210
TRA L9P3 RESET INT REG
L20P4 CLA CHAR
L20P5 CIO 120 TYPE CHAR
STO VAR5 FOR ERROR INFO
CLA H20P4
STO VAR4
CIO 154
L20P6 XOR PATN
TNZ L28P6
L21P1 CLA H21P1
STO VAR4
CIO 214
AND BB CHECK READY LINE
TNZ L21P2
TRA L28P6
L21P2 CLA H21P2
STO VAR4
CLA =O000000004 SET + RESET DO 2
CIO 210
CLA ZERO
CIO 210
HOP H9P3 RESET INT REG
CIO 154
TNZ L28P6
# PAGE 66, SEQUENCE 32270-32830
L21P3 CLA H21P3
STO VAR4
CIO 214
AND BB CHECK READY LINE
TNZ L28P6
L21P4 CDS 0,07
CLA L20P4
ADD KS1 INCREMENT ADDRESS
STO L20P4
CLA L20P6 XOR PATN + CTR
ADD KS1
STO L20P6
CDS 0,12
CLA CTR
ADD K1
STO CTR
SUB STOP
TNZ L20P4 CONTINUE LOOP
L21P5 CLA STOP
SUB =O000000132 IS STOP = 45
TNZ L22P1
TRA L23P1 IF YES
L22P1 CLA STOP
SUB =O000000046 IS STOP = 19
TNZ L22P2
TRA L24P1 IF YES
L22P2 CLA STOP
SUB =O000000020 IS STOP = 8
TNZ L22P3
TRA L26P2 IF YES
L22P3 CLA STOP
SUB =O000000024 IS STOP = 10
TNZ L27P1
L22P4 STO CTR RESET CTR
CLA =O000000014 6
STO STOP
CDS 0,07
CLA L20P5
AND KX1 REMOVE ADDRESS
XOR KX2 = CIO 134
STO L20P5
CDS 0,12
CLA H22P4 CARRIAGE CONTROL
STO VAR4
TRA L20P4
L23P1 CLA H23P1
STO VAR4
CLA H23P5
STO VAR1
CLA C45
CIO 120 FIRST UPPER CASE CHAR
STO VAR5
CIO 154 INT REG
XOR =O400000000
TNZ L28P6
L23P2 CLA H23P2
STO VAR4
# PAGE 67, SEQUENCE 32840-33400
CIO 214 READY LINE
AND BB
TNZ L23P3
TRA L28P6
L23P3 CLA H23P3
STO VAR4
TRA L20P2A DELAY 87.5 MSEC.
CIO 154
XOR P45 1,5,6,9
TNZ L28P6
L23P4 STO CTR RESET CTR
CLA =O000000046 19
STO STOP
CLA H20P3
STO VAR1
TRA L21P1
L24P1 CLA H24P1
STO VAR4
CLA H23P5
STO VAR1
L24P2 CLA CHAR
CIO 120 SET LOWER CASE FROM UPPER CASE
STO VAR5
CIO 154
XOR =O200000000
TNZ L28P6
L24P3 CLA H24P3
STO VAR4
CIO 214 READY LINE
AND BB
TNZ L24P4
TRA L28P6
L24P4 CLA H24P4
STO VAR4
TRA L20P2A DELAY 87.6 MSEC.
CIO 154
XOR =O371000000
TNZ L28P6
L24P5 CLA H24P5
STO VAR4
CLA =O000000020 SET AND RESET DO4
CIO 210
CLA ZERO
CIO 210
TRA L9P3 RESET INT REG
CIO 214 READY LINE
AND BB
TNZ L28P6
* TEST OCTAL MODE
L25P1 STO CTR RESET CTR
CLA H25P1
STO VAR4
CLA =O000000020 8
STO STOP
CDS 0,07
CLA L20P5
AND KX1 REMOVE ADDRESS
# PAGE 68, SEQUENCE 33410-33920
XOR KX3 = CIO 130
STO L20P5
CDS 0,12
CLA C60 SET UPPER CASE
CIO 120
STO VAR5
TRA L20P2A DELAY 87.6 MSEC.
CIO 154
XOR =O511000000 1,3,6,9
TNZ L28P6
* BEGIN OCTAL
L25P2 CLA H25P2
STO VAR4
CLA =O000000004 SET AND RESET DO 2
CIO 210
CLA ZERO
CIO 210
TRA L9P3 RESET INT REG
CLA C64 OCTAL 1
CIO 130
STO VAR5
CIO 154
XOR =O200000000
TNZ L28P6
L25P3 CLA H25P3
STO VAR4
CIO 214
AND BB READY LINE
TNZ L26P1
TRA L28P6
L26P1 CLA H26P1
STO VAR4
TRA L20P2A DELAY 87.6 MSEC.
CLA H20P3
STO VAR1
CIO 154
XOR =O377000000 2 THRU 9
TNZ L28P6
TRA L21P1
* TYPE DECIMAL
L26P2 STO CTR RESET CTR
CLA H20P3
STO VAR1
CLA =O000000024 10
STO STOP
CDS 0,07
CLA L20P5
AND KX1 REMOVE ADDRESS
XOR KX4 = CIO 124
STO L20P5
CDS 0,12
TRA L20P4
# PAGE 69, SEQUENCE 33940-34500
* TYPEWRITER CONTROL
L27P1 CLA H27P1
STO VAR4
STO VAR1
CLA =O000000010 CARRIAGE AT RIGHT-
CIO 210 HAND MARGIN
CIO 214
AND BB
TNZ L27P2
TRA L28P6
L27P2 CLA H27P2
STO VAR4
CIO 154
XOR =O000020000
TNZ L28P6
L27P3 CLA H27P3
STO VAR4
CLA K1 SET DO 1 AND RESET DO 3
CIO 210
CIO 074 RST INT 14
CIO 154
TNZ L28P6
L28P1 CLA H28P1
STO VAR4
CIO 214
AND BB
TNZ L28P2
TRA L28P6
L28P2 CLA H28P2
STO VAR4
CLA ZERO RST D.O. 1
CIO 210
CIO 214
AND BB
TNZ L28P6
STO VAR4
STO VAR5
TRA L28P3
TRA L29P1 FINISHED
L28P4 CLA CHAR
L28P5 XOR PATN
L28P6 STO 776
TRA L28P6B
ORG ,10,,0,,7,
L28P6A STO 776
L28P6B STO TEMP
CLA 776
STO VAR2
CLA TEMP
HOP H95P1
* RESTORE ORIGINAL INSTRUCTIONS
L28P3 STO 776
CLA L20P4
AND KX1 REMOVE ADDRESS
STO TEMP
CLA L28P4
AND KX6
# PAGE 70, SEQUENCE 34510-35070
XOR TEMP
STO L20P4
CLA L20P5
AND KX1 REMOVE ADDRESS
XOR KX5 = CIO 120
STO L20P5
CLA L20P6
AND KX1 REMOVE ADDRESS
STO TEMP
CLA L28P5
AND KX6
XOR TEMP
STO L20P6
HOP 776
DOG 0,12,
* ERROR RETURN
L23P5 TRA L28P3
TRA L20P2
PATN OCT 171000000 INTERRUPTS SET-A
OCT 061000000 B
OCT 070000000 C
OCT 121000000 D
OCT 130000000 E
OCT 020000000 F
OCT 031000000 G
OCT 111000000 H
OCT 100000000 I
OCT 174000000 J
OCT 064000000 K
OCT 075000000 L
OCT 124000000 M
OCT 135000000 N
OCT 025000000 O
OCT 034000000 P
OCT 114000000 Q
OCT 105000000 R
OCT 062000000 S
OCT 073000000 T
OCT 122000000 U
OCT 133000000 V
OCT 023000000 W
OCT 032000000 X
OCT 112000000 Y
OCT 103000000 Z
OCT 177000000 1 BCD
OCT 067000000 2
OCT 076000000 3
OCT 127000000 4
OCT 136000000 5
OCT 026000000 6
OCT 037000000 7
OCT 117000000 8
OCT 106000000 9
OCT 016000000 0
OCT 007000000 SPECIAL CHARS
OCT 163000000
# PAGE 71, SEQUENCE 35080-35640
OCT 172000000
OCT 002000000
OCT 165000000
OCT 004000000
OCT 160000000
OCT 001000000 SPACE
OCT 000010000 UPPER CASE
P45 OCT 517000000
OCT 106000000
OCT 016000000
OCT 007000000
OCT 032000000
OCT 112000000
OCT 103000000
OCT 163000000
OCT 002000000
OCT 034000000
OCT 114000000
OCT 105000000
OCT 165000000
OCT 004000000
OCT 031000000
OCT 111000000
OCT 100000000
OCT 160000000
OCT 001000000
OCT 177000000 1 OCTAL
OCT 067000000 2
OCT 076000000 3
OCT 127000000 4
OCT 136000000 5
OCT 026000000 6
OCT 037000000 7
OCT 016000000 0
OCT 177000000 DECIMAL 1
OCT 067000000 2
OCT 076000000 3
OCT 127000000 4
OCT 136000000 5
OCT 026000000 6
OCT 037000000 7
OCT 117000000 8
OCT 106000000 9
OCT 016000000 0
OCT 000010000 SPACE - CONTRL OPNS
OCT 000400000 TAB
OCT 000020000 CARR RTN
OCT 000200000 INDEX
OCT 000100000 RED
OCT 000040000 BLACK
H20P2 HPC L20P2
H20P3 HPC L20P3
H20P4 HPC L20P4
H21P1 HPC L21P1
H21P2 HPC L21P2
H21P3 HPC L21P3
H22P4 HPC L22P4
# PAGE 72, SEQUENCE 35650-35810
H23P1 HPC L23P1
H23P2 HPC L23P2
H23P3 HPC L23P3
H23P5 HPC L23P5
H24P1 HPC L24P1
H24P3 HPC L24P3
H24P4 HPC L24P4
H24P5 HPC L24P5
H25P1 HPC L25P1
H25P2 HPC L25P2
H25P3 HPC L25P3
H26P1 HPC L26P1
H27P1 HPC L27P1
H27P2 HPC L27P2
H27P3 HPC L27P3
H28P1 HPC L28P1
H28P2 HPC L28P2
# PAGE 73, SEQUENCE 35830-36390
* BEGINNING OF ROUTINE FIVE
* CHECK PRINTER LOGIC AND INTERFACE
L29P1 CLA LCR5
TMI L29P2
TNZ L45P1A
TRA L2P1
L45P1A TRA L45P1
L29P2 CLA H29P2
STO V1
H29P2 HPC L29P2
V1 SYN VAR1
V2 SYN VAR2
V3 SYN VAR3
V4 SYN VAR4
V5 SYN VAR5
CDS 0,15
CLA H29P4
STO V2
TRA L43P1
CLA ZERO
CIO 170
PRS 775
CIO 164
PRS 775
STO CTR
CLA =O000000200 64 DECIMAL
STO STOP
HOP H9P3 RST INT REG
CLA =O000000040 SET DO 5 PRINTER NOT RUNNING
CIO 210
CIO 214
AND K1 PRTR READY
TNZ L29P3
TRA L42P4
L29P3 CLA H29P3
STO V1
CLA ZERO
CIO 210 RST DO 5
CLA =O000000020
CIO 210 SET DO 4
CIO 214
AND K1
TNZ L29P4
TRA L42P4
L29P4 CLA H29P4
STO V1
CLA H30P1
STO V2
CLA ZERO
CIO 210 RST DO 4
CIO 214
AND K1
TNZ L42P3
L30P1 CLA H30P1
STO V1
CLA H30P2
STO V2
# PAGE 74, SEQUENCE 36400-34960
CIO 170 BCD MODE
CLA CHAR
STO V5
PRS 775
* TEST PRS 775
CIO 154 READ INT REG
XOR PATN1
TNZ L42P3
L30P2 CLA H30P2
STO V1
CLA H30P2A
STO V2
HOP H9P3 RST INT REG
CIO 154
TNZ L42P4
* ENTER BCD LOOP
L30P2A CLA H31P4
STO V1
CLA H31P3
STO V2
TRA L31P3
* TEST PRS MEMORY AND DECODE LOGIC
L31P1 PRS CHAR
STO V5
CIO 154 READ INT REG
L31P2 XOR PATN1
TNZ L42P4
L31P3 CLA CTR
ADD K1
STO CTR
CDS 0,10
CLA L31P1
ADD KS2
STO L31P1
CLA L31P2
ADD KS2
STO L31P2
CDS 0,15
L31P4 HOP H9P3 RST INT REG
CLA CTR
SUB STOP
TNZ L31P1 NOT EQUAL - CONTINUE
* TEST BCD DIGITS 2,3,4
L32P1 PRS =O007700000
STO V5
CLA H32P1
STO V1
# The following line was not present in the original source code.
# It has been added as a workaround for what I believe is a bug
# in the original assembler that I haven't been able to figure out
# how to incorporate into the modern assembler.
DOG 0,15,41 # workaround
H32P1 HPC L32P1
CIO 154
XOR =O774300000 1-7,11,12
TNZ L42P3
L32P2 CLA H32P2
STO V1
HOP H9P3 RST INT REG
PRS =O000077000
STO V5
CIO 154
# PAGE 75, SEQUENCE 36970-37530
XOR =O774300000
TNZ L42P3
L32P3 CLA H32P3
STO V1
HOP H9P3 RST INT REG
PRS =O000000770
STO V5
CIO 154
XOR =O774300000
TNZ L42P3
* TEST PRS 774
L32P4 CLA H32P4
STO V1
HOP H9P3 RST INT REG
CLA ZERO
PRS 774
STO V5
CIO 154
XOR =O004700000 7,10,11,12
TNZ L42P3
L33P1 CLA H33P1
STO V1
CLA K1 SET DO 1
CIO 210
CIO 214
AND K1
TNZ L33P2
TRA L42P3
L33P2 CLA H33P2
STO V1
CLA ZERO
CIO 210 RESET DO 1
CIO 214
AND K1
TNZ L42P3
L33P3 CLA H33P3
STO V1
HOP H9P3 RST INT REG
CIO 154
TNZ L42P3
* TEST OCTAL MODE DECODING
L34P1 CLA ZERO
STO CTR
CDS 0,10
CLA K34P2
AND KX7 RETAIN ADDRESS
STO TEMP
CLA L34P2
AND KX8 REMOVE ADDRESS
XOR TEMP
STO L34P2
CLA K34P3
AND KX7
STO TEMP
CLA L34P3
AND KX8
XOR TEMP
# PAGE 76, SEQUENCE 37540-38100
STO L34P3
CDS 0,15
CIO 164 SET OCTAL MODE
CLA H34P5
STO V1
CLA H34P4
STO V2
CLA =O4 INHIBIT CHECK BIT AT 10,11,12 TIME
CIO 250
L34P2 PRS PRSC
STO V5
CIO 154
L34P3 XOR PATN4
TNZ L42P4
L34P4 CLA CTR
ADD KS1
STO CTR
CDS 0,10
CLA L34P2
ADD KS2
STO L34P2
CLA L34P3
ADD KS2
STO L34P3
CDS 0,15
L34P5 HOP H9P3
CLA CTR
SUB C27
TNZ L34P2
PRSC OCT 0
OCT 111111112
OCT 222222222
OCT 333333332
OCT 444444444
OCT 555555554
OCT 666666666
OCT 777777774
* TEST DIGITS 2 THRU 9 DECODE
L34P6 CLA H34P6
STO V1
PRS =O411111114
ADD ZERO
CIO 154
XOR =O170300000 3-6,11,12
TNZ L42P3
L34P7 CLA H34P7
STO V1
HOP H9P3
PRS =O122222222
ADD ZERO
CIO 154
XOR K1303 3,5,6,11,12
TNZ L42P3
L34P8 CLA H34P8
STO V1
HOP H9P3
# PAGE 77, SEQUENCE 38110-38670
PRS =O244444444
ADD ZERO
CIO 154
XOR =O160300000 3-5,11,12
TNZ L42P3
* TEST CHECK BIT FOR 10,11,12 TIME OCTAL MODE
L34P9 CLA H34P9
STO V1
HOP H9P3
CLA =O2
CIO 250 RESET CHECK BIT INHIBIT
PRS =O41111114
ADD ZERO
CIO 154
XOR =O174300000 3-7,11,12
TNZ L42P3
HOP H9P3
TRA L35P2
K31P1 PRS CHAR
K31P2 XOR PATN1
K34P2 PRS PRSC
K34P3 XOR PATN4
* CARRIAGE CONTROL TESTS
* IMMEDIATE SKIP
ORG ,11,,260,,15,
L35P2 CLA H36P2
H36P2 HPC L36P2
STO V1
CLA H36P1
H36P1 HPC L36P1
STO V2
CLA ZERO
STO CTR
CLA =O000000030 =12
STO STOP
CLA C26 =010000000
STO TEMP
L35P3 CLA TEMP
STO VAR5
CIO 160 CARR CTL
CIO 154
L35P4 XOR PATN2
TNZ L42P4A
L36P1 CLA CTR
ADD K1
STO CTR
CLA K1
CIO 210 SET + RESET D.O.1
CLA ZERO
CIO 210
CLA TEMP
ADD C26 =010000000
STO TEMP
CDS 0,11
CLA L35P4
ADD KS2
# PAGE 78, SEQUENCE 38680-39240
STO L35P4
CDS 0,15
L36P2 HOP H9P3 RST INT REG
CLA CTR
SUB STOP
TNZ L35P3 CONTINUE IN LOOP
L36P3 CLA STOP
SUB =O000000030 IS STOP = 12
TNZ L37P1
* IMMEDIATE SPACE
L36P4 STO CTR RST CTR
CLA =O000000006 =3
STO STOP
CLA C9 =410000000
STO TEMP
TRA L35P3
* SKIP AFTER PRINT
L37P1 CLA H37P5
STO V1
CLA H37P4
STO V2
CLA ZERO
STO CTR
TRA L37P1A
L42P4A HOP H95P1
K35P4 XOR PATN2
ORG ,10,1,,,15,
L37P1A CLA =O000000030 =12
STO STOP
CLA CHAR =610000000
STO TEMP
L37P2 CLA TEMP
STO V5
CIO 160
CLA K1
CIO 210 SET DO 1
CLA ZERO
CIO 210 RST DO 1
CIO 154
L37P3 XOR PATN3
TNZ L42P4
L37P4 CLA CTR
ADD K1
STO CTR
CLA TEMP
ADD C26 =010000000
STO TEMP
CDS 0,10
CLA L37P3
ADD KS1
STO L37P3
CDS 0,15
L37P5 HOP H9P3 RST INT REG
L38P1 CLA CTR
SUB STOP
TNZ L37P2
# PAGE 79, SEQUENCE 39250-39800
L38P2 CLA STOP
SUB =O000000030 =12
TNZ L38P4
L38P3 STO CTR =ZERO
CLA =O000000006 =3
STO STOP
CLA C38 =210000000
STO TEMP
TRA L37P2
* AUTOMATIC CARRIAGE SKIP AND PRINTER READ LINE CHECK
L38P4 CLA H38P4
STO V1
CLA ZERO
STO VAR5
CLA =O000000110 DO 3 CARR BUSY
* DO 6 CHANNEL 12 INDICATOR
CIO 210
CIO 214
AND K1 READY LINE
TNZ L39P1
TRA L42P3
L39P1 CLA H39P1
STO V1
CLA ZERO RESET DO 3,6
CIO 210
CLA K1 SET DO 1 (PRINTING)
CIO 210
CIO 154
XOR =O612020000 1,2,6,8,14
TNZ L42P3
L39P2 CLA H39P2
STO V1
STO V4
CLA ZERO
CIO 210 RESET DO1,DO3
# The following line appears in the original assembly listing,
# but was generated by the assembler rather than being source
# code. It is thus commented-out here.
# TRA** GENERATED TRANSFER
CIO 154
L39P2A XOR =O612020000 1,2,6,8,14
TNZ L42P3
L39P3 CLA H39P3
L39P3A STO V4
CIO 214
AND K1
TNZ L42P3
L39P4 CLA H39P4
STO V1
CLA ZERO
STO VAR4
HOP H9P3 RST INT REG
CIO 154
TNZ L42P3
* BCD MODE PARITY ERROR
L40P1 CLA H40P1
STO V1
CIO 170 SET BCD MODE
# PAGE 80, SEQUENCE 39810-40370
CLA =O000000010 SET DO 3 (CARR BUSY)
CIO 210
CLA =O000000014
CIO 210 SET DO 2 (PARITY ERROR)
CLA =O000000016
CIO 210 SET DO 1 (PROCESSOR RELEASE)
CIO 264
CIO 154
XOR =O001020000 9,14
TNZ L42P3
L40P2 CLA H40P2
STO V1
CLA =O000000010 RST DO1, DO2
CIO 210
PRS ZERO
CIO 154
XOR =O005320000 7,9,11,12,14
TNZ L42P3
L40P3 CLA H40P3
STO V1
CLA ZERO
CIO 210 RST DO 3
PRS 775
CIO 154
XOR =O205320000 2,7,9,11,12,14
TNZ L42P3
L41P1 CLA H41P1
STO V1
HOP H9P3 RST INT REG
CIO 154
TNZ L42P3
* OCTAL MODE - PARITY ERROR DURING PRINT
L41P2 CLA H41P2
STO V1
CIO 164 SET OCTAL MODE
CLA K1 SET DO 1 (PROC. RELEASE)
CIO 210
CLA =O000000006 SET DO 2 (PTY ERROR)
CIO 210
CIO 264
CLA K1 RST DO 2
CIO 210
CLA ZERO
CIO 210 RST DO 1
PRS 775
ADD ZERO
CIO 154
XOR =O725300000 1,2,3,5,7,9,11,12
TNZ L42P3
L41P3 CLA H41P3
STO V1
HOP H9P3
CIO 154
TNZ L42P3
* OCTAL MODE - PARITY ERROR DURING BUFFER LOAD
# PAGE 81, SEQUENCE 40380-40940
L42P1 CLA H42P1
STO V1
CLA =O000000004 SET DO 2
CIO 210
CIO 264
CLA ZERO RST
CIO 210
PRS 775
ADD ZERO
CIO 154
XOR =O525300000 1,3,5,7,9,11,12
TNZ L42P3
L42P2 CLA H42P2
STO V1
HOP H9P3
CIO 154
TNZ L42P3
TRA L43P1
TRA L45P1 TO ROUTINE 6
* TO ERROR ROUTINE
L42P3 STO 776
STO TEMP1
CLA 776
STO VAR2
HOP H9P3
CLA TEMP1
L42P4 TRA L95P1
K37P3 XOR PATN3
# The following line was not present in the original source code.
# It has been added as a workaround for what I believe is a bug
# in the original assembler that I haven't been able to figure out
# how to incorporate into the modern assembler.
DOG 0,15,55 # workaround
H29P3 HPC L29P3
H29P4 HPC L29P4
H30P1 HPC L30P1
H30P2 HPC L30P2
H31P3 HPC L31P3
H31P4 HPC L31P4
H32P2 HPC L32P2
H32P3 HPC L32P3
H32P4 HPC L32P4
H33P1 HPC L33P1
H33P2 HPC L33P2
H33P3 HPC L33P3
H34P4 HPC L34P4
H34P5 HPC L34P5
H34P6 HPC L34P6
H34P7 HPC L34P7
H34P8 HPC L34P8
H34P9 HPC L34P9
H37P4 HPC L37P4
H37P5 HPC L37P5
H38P4 HPC L38P4
H39P1 HPC L39P1
H39P2 HPC L39P2
H39P3 HPC L39P3
H39P4 HPC L39P4
H40P1 HPC L40P1
H40P2 HPC L40P2
H40P3 HPC L40P3
# PAGE 82, SEQUENCE 40950-40990
H41P1 HPC L41P1
H41P2 HPC L41P2
H41P3 HPC L41P3
H42P1 HPC L42P1
H42P2 HPC L42P2
# PAGE 83, SEQUENCE 41010-41570
PATN1 OCT 61430000 A PRTR
OCT 62430000 B
OCT 63430000 C
OCT 64430000 D
OCT 65430000 E
OCT 66430000 F
OCT 67430000 G
OCT 70430000 H
OCT 71430000 I
OCT 41430000 J
OCT 42430000 K
OCT 43430000 L
OCT 44430000 M
OCT 45430000 N
OCT 46430000 O
OCT 47430000 P
OCT 50430000 Q
OCT 51430000 R
OCT 22430000 S
OCT 23430000 T
OCT 24430000 U
OCT 25430000 V
OCT 26430000 W
OCT 27430000 X
OCT 30430000 Y
OCT 31030000 Z
OCT 01430000 1 BCD
OCT 02430000 2
OCT 03430000 3
OCT 04430000 4
OCT 05430000 5
OCT 06430000 6
OCT 07430000 7
OCT 10430000 8
OCT 11430000 9
OCT 12430000 0
OCT 13430000 SPCL CHARS
OCT 20430000
OCT 21430000
OCT 33430000
OCT 40430000
OCT 53430000
OCT 60430000
OCT 73430000
OCT 00430000
OCT 14430000
OCT 15430000
OCT 16430000
OCT 17430000
OCT 32430000
OCT 34430000
OCT 35430000
OCT 36430000
OCT 37430000
OCT 52430000
OCT 54430000
OCT 55430000
# PAGE 84, SEQUENCE 41580-42040
OCT 56430000
OCT 57430000
OCT 72430000
OCT 74430000
OCT 75430000
OCT 76430000
OCT 77430000 END BCD
PATN4 OCT 12430000 0 OCTAL
OCT 13030000 1
OCT 12030000 2
OCT 13430000 3
OCT 16030000 4
OCT 17430000 5
OCT 16430000 6
OCT 17030000 7
PATN2 OCT 01210000 CHNL.1 - IMMED. SKIP
OCT 02210000 2
OCT 03610000 3
OCT 04210000 4
OCT 05610000 5
OCT 06610000 6
OCT 07210000 7
OCT 10210000 8
OCT 11610000 9
OCT 12610000 10
OCT 13210000 11
OCT 14610000 12
OCT 41610000 1 IMMED. SPACE
OCT 42610000 2
OCT 43210000 3
* SKIP AFTER PRINT CHANNEL
PATN3 OCT 61210000 1
OCT 62210000 2
OCT 63610000 3
OCT 64210000 4
OCT 65610000 5
OCT 66610000 6
OCT 67210000 7
OCT 70210000 8
OCT 71610000 9
OCT 72610000 10
OCT 73210000 11
OCT 74610000 12
* SPACE AFTER PRINT
OCT 21610000 1
OCT 22610000 2
OCT 23210000 3
# PAGE 85, SEQUENCE 42060-42410
* RESTORE ORIGINAL INSTRUCTIONS
L43P1 STO 776
CLA 776
STO HRTRN
CDS 0,10
CLA K31P1
STO TEMP
CLA L31P1
TRA L1P1C
STO L31P1
CLA K31P2
STO TEMP
CLA L31P2
TRA L1P1C
STO L31P2
CDS 0,11
CLA K35P4
STO TEMP
CLA L35P4
TRA L1P1C
STO L35P4
CDS 0,10
CLA K37P3
STO TEMP
CLA L37P3
TRA L43P2
STO L37P3
HOP HRTRN
* RESTORE SYLLABLE 1 INSTRUCTION
L43P2 STO 776
AND KX1 REMOVE ADDRESS
STO TEMP1
CLA TEMP
AND KX6 KEEP ADDRESS
XOR TEMP1
HOP 776
# PAGE 86, SEQUENCE 42430-42990
* BEGINNING OF ROUTINE SIX
* EXERCISE CALCOMP DIGITAL INCREMENTAL PLOTTER
ORG ,11,1,,,15,
L45P1 CLA LCR6
TMI L45P2
TNZ L50P1A
TRA L2P1
L50P1A TRA L50P1
H45P2 HPC L45P2
L45P2 CLA H45P2
STO VAR1
CLA H50P1
H50P1 HPC L50P1
STO VAR2
CLA K1
CIO 150 RAISE PEN
TRA L47P1B DELAY 0.11 SEC
CIO 214
AND K2
TNZ L45P3A
STO V4 =0
CLA KMAXMA
KMAXMA OCT 400003774
KMAXM OCT 400001774
CIO 144 CARR RIGHT
TRA L47P3
CIO 214
AND K2
K2 OCT 000000004
TNZ L45P3A
L45P3 CLA K2
CIO 150 LOWER PEN
TRA L47P1B DELAY 0.11 SEC
CIO 214
AND K2
TNZ L45P3A
CLA KMAXPA
KMAXPA OCT 000003774
KMAXP OCT 000001774
CIO 140 DRUM DOWN
CLA ZERO
CIO 144 PLOT
CIO 214
AND K2 CHECK READY
TNZ L45P3B
L45P3A STO 776
STO TEMP
CLA 776
STO V4
CLA TEMP
HOP H95P1
L45P3B TRA L47P3
L45P4 CLA KMAXP
CIO 144 CARR LEFT
TRA L47P4
L45P5 CLA KHP
KHP OCT 000000776
# PAGE 87, SEQUENCE 43000-43560
CIO 140 DRUM DOWN
CLA KHM
KHM OCT 400000776
CIO 144 CARR RIGHT
TRA L47P5
L46P1 CLA KHM
CIO 140 DRUM UP
CLA KHM
CIO 144 CARR RIGHT
TRA L47P5
L46P2 CLA KMAXM
CIO 140 DRUM UP
CLA KMAXP
CIO 144 CARR LEFT
TRA L47P4
L46P3 CLA KMAXM
CIO 144 CARR RIGHT
TRA L47P4
L46P4 CLA KMAXP
CIO 140 DRUM UP
CIO 144 CARR LEFT
TRA L47P4
L46P5 CLA KMAXM
CIO 140 DRUM UP
CLA ZERO
CIO 144
TRA L47P4
L46P6 CLA K1
CIO 150 RAISE PEN
CLA KHM CARR RIGHT
CIO 144
TRA L47P5
L46P7 CLA KHP DRUM DOWN
CIO 140
CLA ZERO
CIO 144
TRA L47P5
L47P1 CLA K2
CIO 150 LOWER PEN
TRA L47P1B DELAY 0.11 SEC
TRA L47P1C
L47P1B STO 777
CLA =O000002466 DELAY 110 MSEC.
L47P1A SUB K1
TNZ L47P1A
HOP 777
L47P1C CLA H47P1
H47P1 HPC L47P1
STO VAR1
CLA H47P2
H47P2 HPC L47P2
STO VAR2
CIO 214 CHECK READY
AND K2
TNZ L45P3A
L47P2 CLA KHM
CIO 144 CARR RIGHT
# PAGE 88, SEQUENCE 43570-44130
TRA L47P5
CLA K1
CIO 150 RAISE PEN
CLA =O000002260 600 DEC.
CIO 140 DRUM DOWN
CLA =O000002400 640 DEC.
CIO 144 CARR. LEFT
CLA =O000000014
STO CTR
L48P2 TRA L48P1 WAIT
CLA K2 LOWER PEN
CIO 150
TRA L48P1 WAIT
CLA K2 DRUM DOWN 2
CIO 140
CLA ZERO
CIO 144
TRA L48P1
CLA K1
CIO 150 RAISE PEN
TRA L48P1
CLA =O400000010 DRUM UP 4
CIO 140
CLA ZERO
CIO 144
TRA L48P1
CLA K2 LOWER PEN
CIO 150
TRA L48P1
CLA =O400000004 CARR. RIGHT 2
CIO 144
TRA L48P1
CLA K1 RAISE PEN
CIO 150
TRA L48P1
CLA BB CARR LEFT 4
CIO 144
CLA CTR
SUB K1
STO CTR
TNZ L48P2
TRA L48P1 WAIT
CLA K2 LOWER PEN
CIO 150
CLA =O000000014
STO CTR
L48P3 TRA L48P1 WAIT
CLA K2 DRUM DOWN 2
CIO 140
CIO 144 CARR LEFT 2
TRA L48P1 WAIT
CLA =O400000004 DRUM UP 2
CIO 140
CLA K2 CARR LEFT 2
CIO 144
TRA L48P1 WAIT
CLA =O400000004
# PAGE 89, SEQUENCE 44140-44530
CIO 140 DRUM UP 2
CIO 144 CARR RIGHT 2
TRA L48P1 WAIT
CLA =O400000004 DRUM UP 2
CIO 140
CLA K2 CARR LEFT 2
CIO 144
CLA CTR
SUB K1
STO CTR
TNZ L48P3
TRA L48P1 WAIT
CLA K1 RAISE PEN
CIO 150
TRA L48P1 WAIT
CLA K324 424 DECIMAL
CIO 144
# The following line appears in the original assembly listing,
# but was generated by the assembler rather than being source
# code. It is thus commented-out here. As I haven't figured
# out yet how to get the modern assembler to insert the identical
# TRA** generated by the original assembler, there are also a
# couple of added workaround lines to explicitly produce the
# effect of the TRA**.
# TRA** GENERATED TRANSFER
TRA WKRND2 # workaround
ORG 0,11,1,260,0,15, # workaround
WKRND2 TRA L48P1 WAIT # the lhs is an added workaround
TRA L50P1
ORG ,11,1,264,,15,
L47P3 STO 776
CLA =O000131002 DELAY 3.76 SEC.
L47P3A SUB K1
TNZ L47P3A
HOP 776
L47P4 STO 776
CLA =O000054402 DELAY 1.88 SEC.
L47P4A SUB K1
TNZ L47P4A
HOP 776
L47P5 STO 776
CLA =O000026202 DELAY .94 SEC.
L47P5A SUB K1
TNZ L47P5A
HOP 776
L48P1 STO 776
CIO 214 WAIT FOR READY
AND K2
TNZ *-2
HOP 776
# PAGE 90, SEQUENCE 44550-45110
* BEGINNING OF ROUTINE SEVEN
* EXERCISE TYPEWRITER
ORG ,11,,,,11,260
L50P1 CLA LCR7
TMI L50P2
TNZ L60P1
TRA L2P1
* SET RIGHT MARGIN BETWEEN 120 AND 124
* SET LEFT MARGIN AT 0
* SET TAB AT 10
KL1 CLA LINE1
KL2 CLA LINE2
KL3 CLA LINE3
KL4 CLA LINE4
KL5 CLA LINE5
KL6 CLA LINE6
L50P2 TRA L98P4 CARR RTN
TRA L52P1 TAB
CIO 214
AND BB
TNZ *-2
CLA =O200000000 SET BLACK RIBBON
CIO 134
CLA =O000000020
STO STOP
CLA KL1
TRA L98P3 TYPE LINE 1
L50P3 TRA L98P4 CARR RTN
TRA L98P5 INDEX
TRA L52P1 TAB
CLA =O000000020
STO STOP
CLA KL2
TRA L98P3 TYPE LINE 2
L50P4 TRA L98P4 CARR RTN
TRA L98P5 INDEX
TRA L52P1 TAB
CLA =O000000024
STO STOP
CLA KL3
TRA L98P3 TYPE LINE 3
L51P1 CLA =O000000240 80 SPACES
TRA L98P1 SPACE
* SHOULD HIT RIGHT MARGIN AND EXECUTE AUTOMATIC CARRIAGE RETURN
* AND COMPLETE SPACING
TRA L52P1
CLA =O000000016
STO STOP
CLA KL4
TRA L98P3 TYPE LINE 4
L51P2 TRA L98P4 CARR RTN
TRA L98P5 INDEX
TRA L52P1 TAB
CLA =O000000014
STO STOP
CLA KL5
TRA L98P3 TYPE 1ST PART LINE 5
# PAGE 91, SEQUENCE 45120-45600
CLA LINE5A
TRA L98P2
L51P3 TRA L98P4 CARR RTN
TRA L98P5 INDEX
TRA L52P1 TAB
CLA =O000000016
STO STOP
CLA KL6
TRA L98P3 TYPE 1ST PART LINE 6
CIO 214
AND BB
TNZ *-2
CLA =O100000000 SET RED RIBBON
CIO 134
CLA =O000000006 SPACE 3
TRA L98P1
CLA LINE6A TYPE 2ND PART LINE 6
TRA L52P2
CLA LINE6B
TRA L52P2
TRA L98P4 CARR RTN
TRA L60P1
* TAB CONTROL
L52P1 STO 776
CIO 214
AND BB
TNZ *-2
CLA =O010000000
CIO 134
HOP 776
* TYPE DECIMAL NUMBER
L52P2 STO 776
STO TEMP
CLA =O000000014
STO STOP
L52P2A CIO 214
AND BB
TNZ *-2
CLA TEMP
CIO 124
SHL 4
STO TEMP
CLA STOP
SUB K1
STO STOP
TNZ L52P2A
HOP 776
# PAGE 92, SEQUENCE 45620-46180
* BEGINNING OF ROUTINE EIGHT
* EXERCISE PRINTER
L60P1 CLA LCR8
TMI L60P2B
TNZ NAB1B
TRA L2P1
L60P2B TRA L60P2
NAB1B TRA NAB1
ORG ,4,1,2,,5,11
L60P2 CLA C26 IMMED SKIP CH. 1
CIO 160
CLA ZERO
STO CTR2
STO CTR3
STO PGNR
TRA L61P5
L60P2A CLA ZERO
STO CTR
STO CTR1
CLA PGNR
ADD =O000001
STO PGNR
CIO 214
AND K1
TNZ *-2
* PRINT PAGE NUMBER AND HEADING
CIO 170 SET BCD MODE
CLA =O000000024 TEN
L60P2J STO STOP
PRS ZERO
CLA STOP
SUB K1
TNZ L60P2J
PRS KK
PRS KK+1
PRS KK+2
PRS KK+3
PRS KK+4
PRS KK+5
PRS KK+6
PRS KK+7
PRS KK+8
CLA =O000000020 =8
L60P2C STO STOP
PRS ZERO
CLA STOP
SUB K1
TNZ L60P2C
PRS KL
PRS KL+1
CLA PGNR
SUB =O000012 TEN
TMI L60P2E
CLA PGNR
SUB =O000024 20
TMI L60P2F
TNZ *+2
# PAGE 93, SEQUENCE 46190-46710
CLA =O000012
XOR =O0002 1ST DIGIT = 2
L60P2D PRS 775
CLA PGNR
SUB =O000013 = 11
TMI L60P2G
STO TEMP
SUB =O000012 TEN
TMI L60P2H
PRS 774
CIO 214
AND K1
TNZ *-2
CLA =O13 IMMED SKIP CH 11
CIO 160
TRA L60P3
L60P2E CLA PGNR
TRA L60P2D
L60P2F CLA PGNR
SUB =O000012 TEN
TNZ *+2
CLA =O000012
XOR =O0001
TRA L60P2D
L60P2G PRS 774
CIO 214
AND K1
TNZ *-2
CLA PGNR
ADD =O000001
SHL 12
CIO 160 IMMED SKIP CH 2- 11
TRA L60P3
L60P2H CLA TEMP
ADD =O000002
SHL 12
XOR =O6
CIO 160 SKIP AFTER PRINT CH 2-11
PRS 774
TRA L60P3
L60P3 CIO 214
AND K1 CHECK PRINTER READY
TNZ L60P3
L60P3A PRS KA
CLA CTR1
ADD KS1
STO CTR1
CDS 0,4
CLA L60P3A
ADD KS1
STO L60P3A
CDS 0,5
CLA CTR
# PAGE 94, SEQUENCE 46720-47260
ADD KS1
STO CTR
SUB C29 = 16
TNZ L60P5
L60P4 STO CTR
TRA L61P5
L60P5 CLA CTR1
SUB =O074000000 = 30
TNZ L60P3
L61P1 STO CTR1
PRS 774 PRINT LINE
CIO 214
AND K1
TNZ *-2
CLA CTR2
ADD KS1
STO CTR2
SUB =O016000000 =7
TMI L61P1C
TNZ L61P4
TRA L61P2A
L61P1C CLA CTR2
AND C26 =010000000
TNZ L61P1A
CLA CTR2
SHL 2
XOR C40
CIO 160 SPACE
TRA L60P3
L61P1A CLA CTR2
SUB =O006000000
SHL 2
XOR C37 =200000000
CIO 160
TRA L60P3
L61P2A CLA PGNR
SUB =O000025 = 21
TNZ L60P3
CLA =O74 SKIP AFTER PRINT CH 12
CIO 160
TRA L60P3
L61P4 CLA ZERO
STO CTR2
CLA CTR3
ADD KS1
STO CTR3
SUB =O02
TNZ *+2
STO CTR3
TRA L61P5
TRA L62P1
L61P5 STO 776
CDS 0,4
CLA K61P3A
AND KX6 RETAIN ADDRESS
# PAGE 95, SEQUENCE 47270-47830
ADD CTR3 = CLA C(LA + CTR3)
STO TEMP
CLA L61P3A
AND KX1 REMOVE ADDRESS
XOR TEMP
STO L61P3A
L61P3A CLA LA
AND KX6 RETAIN ADDRESS
STO TEMP
CLA L60P3A PRS INSTRUCTION
AND KX1 REMOVE ADDRESS
XOR TEMP COMBINE ADDRESS AND OP CODE
STO L60P3A
HOP 776
K61P3A CLA LA
DOG 0,5,
LA PRS KA
PRS KB
PRS KC
PRS KD
PRS KE
PRS KF
PRS KG
PRS KH
L62P1 CLA PGNR
SUB =O000013 = 11
TMI L62P5
TNZ L62P2
CLA =O14 IMMED SKIP CH 12
CIO 160
CIO 214
AND K1
TNZ *-2
TRA L62P5
L62P2 CLA PGNR
SUB =O000025 =21
TNZ L62P3
TRA L62P5
L62P3 CLA =O61 SKIP AFTER PRINT CH 1
CIO 160
* PRINT OCTAL LINE
L62P5 CIO 164 SET OCTAL MODE
PRS KJ LOAD BUFFERS
ADD ZERO
PRS KJ+1
ADD ZERO
PRS KJ+2
ADD ZERO
PRS KJ+3
ADD ZERO
PRS KJ+4
ADD ZERO
PRS KJ+5
ADD ZERO
PRS KJ+6
ADD ZERO
# PAGE 96, SEQUENCE 47840-48200
PRS KJ+7
ADD ZERO
PRS KJ+8
ADD ZERO
PRS KJ+9
ADD ZERO
PRS 774
CIO 214 CHECK READY LINE
AND K1
TNZ *-2
CLA PGNR
SUB =O000013 = 11
TMI L62P4 LESS THAN 11
SUB =O000012 =10
TNZ L60P2A
TRA NAB1 FINISHED
L62P4 CLA =O01 IMMED SKIP CH 1
CIO 160
TRA L60P2A
# The following line was not present in the original source
# code. It is present as a workaround for a bug in the original
# assembler that I have not been able to duplicate in the
# modern assembler.
DOG 0,5,12 # workaround
KA OCT 141516170
OCT 323536370
OCT 525556570
OCT 727576770
OCT 132040530
OCT 336021340
OCT 745473000
BCI ^ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456789$
KB OCT 111415160
OCT 173235360
OCT 375255560
OCT 577275760
OCT 771320400
OCT 533360210
OCT 347454730
BCI ^ ABCDEFGHIJKLMNOPQRSTUVWXYZ012345678$
KC OCT 101114150
# PAGE 97, SEQUENCE 48210-48470
OCT 161732350
OCT 363752550
OCT 565772750
OCT 767713200
OCT 405333600
OCT 213474540
BCI ^. ABCDEFGHIJKLMNOPQRSTUVWXYZ01234567$
KD OCT 071011140
OCT 151617320
OCT 353637520
OCT 555657720
OCT 757677130
OCT 204053330
OCT 602134740
BCI ^*. ABCDEFGHIJKLMNOPQRSTUVWXYZ0123456$
KE OCT 060710110
OCT 141516170
OCT 323536370
OCT 525556570
OCT 727576770
OCT 132040530
OCT 336021340
BCI ^)*. ABCDEFGHIJKLMNOPQRSTUVWXYZ012345$
KF OCT 050607100
OCT 111415160
OCT 173235360
OCT 375255560
# PAGE 98, SEQUENCE 48480-48740
OCT 577275760
OCT 771320400
OCT 533360210
BCI ^()*. ABCDEFGHIJKLMNOPQRSTUVWXYZ01234$
KG OCT 040506070
OCT 101114150
OCT 161732350
OCT 363752550
OCT 565772750
OCT 767713200
OCT 405333600
BCI ^/()*. ABCDEFGHIJKLMNOPQRSTUVWXYZ0123$
KH OCT 030405060
OCT 071011140
OCT 151617320
OCT 353637520
OCT 555657720
OCT 757677130
OCT 204053330
BCI ^+/()*. ABCDEFGHIJKLMNOPQRSTUVWXYZ012$
KJ OCT 012345670
OCT 123456700
OCT 234567012
OCT 345670122
OCT 456701234
OCT 567012344
OCT 670123456
# PAGE 99, SEQUENCE 48750-48790
OCT 701234566
OCT 012345670
OCT 123456700
KK BCI ^ROUTINE 8 EXERCISE 1443 PRINTER$
KL BCI ^PAGE NR $
# PAGE 100, SEQUENCE 48810-49370
* ERROR ROUTINE
# The 50-word table at ERR (see paragraph 7-34 of the PTC
# documentation) can store up to 10 errors, as 5-word blocks.
# The first error encountered is stored at ERR through ERR+4,
# the second at ERR+5 through ERR+9, and so on. This is
# self-modifying code. You'll notice that as written, the STO
# instructions (at L95P7 and at L95P2-L95P5) put data into the
# error table at ERR through ERR+4, but farther down in the code
# (at L96P1) all of these STO's are overwritten with different
# STO instructions operating 5 words higher in the ERR table.
# At the 11th error (there is no test in the code for overflowing
# the end of the ERR table!), the modified code then at L95P7
# will overwrite the instruction L95P7+1 with ERR-table data,
# and the program will probably crash. -- RSB 2020.
ORG ,16,,1,,16,212
ERR BSS 50
L95P1 CIO 240 SET PTC ERROR LAMP
L95P7 STO ERR+2
CLA VAR1
L95P2 STO ERR+1
CLA VAR3
L95P3 STO ERR
CLA VAR4
L95P4 STO ERR+3
CLA VAR5
L95P5 STO ERR+4
CLA LC5
TNZ *+4
CLA VAR3
STO LC9
CLA LC5
ADD K1
STO LC5
SUB =O000000024
TNZ L95P6
CLA K77
STO LC6
L95P6 CLA VAR3
XOR LC9
TNZ L96P1
CLA LC5
STO LC7 ERROR COUNT FIRST PASS
L96P1 CLA LC6
TMI L96P2
CLA L95P7
ADD =O000000500
STO L95P7
CLA L95P2
ADD =O000000500
STO L95P2
CLA L95P3
ADD =O000000500
STO L95P3
CLA L95P4
ADD =O000000500
STO L95P4
CLA L95P5
ADD =O000000500
STO L95P5
L96P2 CLA LC2
TMI L96P3
HOP VAR2
L96P3 HOP VAR1
L1P1A1 CLA K95P3
STO TEMP
CLA L1P1B
TRA L1P1C
STO L1P1B
CLA =O000000144
STO STOP
# PAGE 101, SEQUENCE 49380-49940
CLA ZERO
L1P1B STO ERR
CLA L1P1B
ADD =O000000100
STO L1P1B
CLA STOP
SUB K1
STO STOP
TNZ L1P1B-1
STO VAR3
STO LC5
STO LC6
STO LC7
CIO 210
CLA K95P1
STO TEMP
CLA L95P7
TRA L1P1C
STO L95P7
CLA K95P2
STO TEMP
CLA L95P2
TRA L1P1C
STO L95P2
CLA K95P3
STO TEMP
CLA L95P3
TRA L1P1C
STO L95P3
CLA K95P4
STO TEMP
CLA L95P4
TRA L1P1C
STO L95P4
CLA K95P5
STO TEMP
CLA L95P5
TRA L1P1C
STO L95P5
HOP H2P1
ORG ,16,1,,,16,
L1P1C STO 776
AND =O777740036
STO TEMP1
CLA TEMP
AND =O000037740
XOR TEMP1
HOP 776
ORG ,16,0,142,,16,
K95P1 STO ERR+2
K95P2 STO ERR+1
K95P3 STO ERR
K95P4 STO ERR+3
K95P5 STO ERR+4
K97P3 CLA KHDG
K97P5 CLA KHDG1
K97P5A CLA KHDG2
# PAGE 102, SEQUENCE 49950-50500
* TYPE BCD WORDS
L98P3 STO 776
AND =O000037776 SAVE SYLL 0
STO TEMP
CLA L98P3A
AND =O777740000 SAVE SYLL 1
XOR TEMP COMBINE SYLLABLES
STO L98P3A
L98P3C CLA =O000000010
STO TEMP1
L98P3A CLA WORD
STO TEMP
L98P3B CIO 214
AND BB
TNZ L98P3B
CLA TEMP
CIO 120
SHL 6
STO TEMP
CLA TEMP1
SUB K1
STO TEMP1
TNZ L98P3B
CLA L98P3A
ADD KS2 INCREMENT ADDRESS
STO L98P3A
CLA STOP
SUB K1
STO STOP
TNZ L98P3C
HOP 776
ORG ,16,1,7,,16,
* ERROR READOUT
L97P1 CLA LC3
TMI L97P2
TRA L99P1
L90P1A TRA L90P1 TO PRINTER ROUTINE
* TYPE ERROR INFORMATION
L97P2 CIO 220 B SWITCHES
TMI L90P1A USE PRINTER
TRA L98P4 CARRIAGE RETURN
CLA K97P4A
STO TEMP
CLA L97P4A
HOP H43P2
STO L97P4A
* TYPE HEADING
L97P3 CLA =O000000024 INDENT 10 SPACES
TRA L98P1
CLA =O000000034 14 4-CHAR WORDS
STO STOP
CLA K97P3 ADDRESS OF HEADING
TRA L98P3
TRA L98P4 CARR RTN
TRA L98P5 INDEX 1
* TYPE OCTAL ERROR INFORMATION
# PAGE 103, SEQUENCE 50510-50980
CLA =O000000024 10 LINES
STO CTR
L97P4 CLA =O000000024 INDENT 10
TRA L98P1
CLA =O000000012 5 WORDS PER LINE
STO TEMP1
L97P4A CLA ERR
TRA L98P2
CLA L97P4A
ADD KS1 INCREMENT ADDRESS
STO L97P4A
CLA TEMP1
SUB K1
STO TEMP1
TNZ L97P4A
TRA L98P4 CARR RTN
TRA L98P5 INDEX 1
CLA CTR
SUB K1
STO CTR
TNZ L97P4
* TYPE ERROR COUNT
L97P5 CLA =O000000024 INDENT 10
TRA L98P1
CLA =O000000014 6 4-CHAR WORDS
STO STOP
CLA K97P5 ADDRESS OF FIRST WORD
TRA L98P3
CLA LC5
TRA L98P2
TRA L98P4 CARR RTN
TRA L98P5 INDEX 1
CLA =O000000024 INDENT 10
TRA L98P1
CLA =O000000014 6 4-CHAR WORDS
STO STOP
CLA K97P5A ADDRESS OF FIRST WORD
TRA L98P3
CLA LC7
TRA L98P2
TRA L98P4 CARR RTN
TRA L98P5 INDEX
CIO 214
AND =O000004000 B15
TNZ L97P2
TRA L1P1
K97P4A CLA ERR
# The following line was not present in the original source code.
# It has been added as a temporary workaround for what I believe
# may be a bug in the original assembler that I have not yet
# figured out how to reproduce in the modern assembler.
DOG 0,16,276
KHDG BCI ^ PASS NR LOCATION ACCUM VAR4 VAR5$
# PAGE 104, SEQUENCE 50990-51350
KHDG1 BCI ^TOTAL ERROR COUNT $
KHDG2 BCI ^ERROR COUNT FIRST PASS $
* SPACE PER NUMBER IN ACCUMULATOR
L98P1 STO 776
STO N
L98P1A CIO 214
AND BB
TNZ *-2
CLA =O400000000
CIO 134
CLA N
SUB K1
STO N
TNZ L98P1A
HOP 776
* TYPE OCTAL WORD IN ACCUMULATOR
L98P2 STO 776
STO WORD
CLA 776
STO HRTRN
CLA =O000000022
STO NINE
L98P2A CIO 214
AND BB
TNZ *-2
CLA WORD
CIO 130
SHL 3
STO WORD
CLA NINE
SUB K1
STO NINE
TNZ L98P2A
CLA =O000000006
# PAGE 105, SEQUENCE 51360-51920
TRA L98P1 TO SPACE 3 PLACES
HOP HRTRN
* CARRIAGE RETURN
L98P4 STO 776
CIO 214
AND BB
TNZ *-2
CLA =O020000000
CIO 134
HOP 776
* INDEX CARRIAGE ONE LINE
L98P5 STO 776
CIO 214
AND BB
TNZ *-2
CLA =O040000000
CIO 134
HOP 776
K90P3 PRS KHDG
K90P5 PRS KHDG1
K90P6 PRS KHDG2
ORG ,10,1,304,,16,
L99P1 CIO 114 SET SINGLE STEP
CLA ERR
CLA ERR+1
CLA ERR+2
CLA ERR+3
CLA ERR+4
CLA ERR+5
CLA ERR+6
CLA ERR+7
CLA ERR+8
CLA ERR+9
CLA ERR+10
CLA ERR+11
CLA ERR+12
CLA ERR+13
CLA ERR+14
CLA ERR+15
CLA ERR+16
CLA ERR+17
CLA ERR+18
CLA ERR+19
CLA ERR+20
CLA ERR+21
CLA ERR+22
CLA ERR+23
CLA ERR+24
CLA ERR+25
CLA ERR+26
CLA ERR+27
CLA ERR+28
CLA ERR+29
# PAGE 106, SEQUENCE 51930-52490
CLA ERR+30
CLA ERR+31
CLA ERR+32
CLA ERR+33
CLA ERR+34
CLA ERR+35
CLA ERR+36
CLA ERR+37
CLA ERR+38
CLA ERR+39
CLA ERR+40
CLA ERR+41
CLA ERR+42
CLA ERR+43
CLA ERR+44
CLA ERR+45
CLA ERR+46
CLA ERR+47
CLA ERR+48
CLA ERR+49
TRA L99P1
* TO RESUME NORMAL OPERATION HIT MACHINE RESET
ORG ,6,1,120,,16,
* PRINT ERROR INFORMATION
L90P1 TRA L94P3 CHECK READY
PRS 774 CLEAR BUFFERS
TRA L94P3 CHECK READY
CLA C26 SKIP TO CHANNEL 1
CIO 160
CIO 170
L90P2 TRA L94P3
PRS ZERO
PRS ZERO
PRS ZERO
* PRINT HEADING
L90P3 CLA =O000000034
STO STOP
CLA K90P3
TRA L94P1 LOAD BUFFERS
PRS 774
TRA L94P3 CHECK READY
CLA =O410000000 SPACE 1
CIO 160
CDS 0,6
CLA K90P4A
AND KX6
STO TEMP
CLA L90P4A
AND KX1
XOR TEMP
STO L90P4A RESTORE ORIGINAL ADDRESS
CDS 0,16
CLA =O000000024 TEN
STO STOP
L90P4 CIO 170 SET BCD MODE
CLA =O000000012 FIVE
STO TEMP
# PAGE 107, SEQUENCE 52500-53060
PRS ZERO
PRS ZERO
PRS ZERO
CIO 164 SET OCTAL MODE
L90P4A PRS ERR
CDS 0,6
CLA L90P4A
ADD KS1
STO L90P4A
CDS 0,16
CLA TEMP
SUB K1
STO TEMP
TNZ L90P4A
PRS 774 PRINT OCTAL LINE
TRA L94P3
CLA =O410000000
CIO 160
TRA L94P3
CLA STOP
SUB K1
STO STOP
TNZ L90P4
CIO 170 SET BCD MODE
PRS ZERO
PRS ZERO
PRS ZERO
CLA =O000000014 SIX
STO STOP
CLA K90P5
TRA L94P1
CIO 164 SET OCTAL MODE
PRS LC5
ADD ZERO
PRS 774 PRINT TOTAL ERROR COUNT
TRA L94P3
CLA =O410000000
CIO 160
CIO 170 SET BCD MODE
TRA L94P3 CHECK READY
L90P6 PRS ZERO
PRS ZERO
PRS ZERO
CLA =O000000014 SIX
STO STOP
CLA K90P6
TRA L94P1
CIO 164 SET OCTAL MODE
PRS LC7
ADD ZERO
PRS 774 PRINT ERROR COUNT FIRST PASS
HOP H2P1 FINISHED
K90P4A PRS ERR
* LOAD BUFFERS WITH BCD LINE OF PRINT
L94P1 STO 776
AND KX6
# PAGE 108, SEQUENCE 53070-53300
STO TEMP
CDS 0,6
CLA L94P2
AND KX1
XOR TEMP
STO L94P2
CDS 0,16
L94P2 PRS WORD
CLA STOP
SUB K1
STO STOP
TNZ *+2
HOP 776
CDS 0,6
CLA L94P2
ADD KS1
STO L94P2
CDS 0,16
TRA L94P2
L94P3 STO 776
CIO 214
AND K1
TNZ *-2
HOP 776
# PAGE 109, SEQUENCE 53320-53880
ORG 1,,,10,1,10,
JAB1 CLA LCR9
TMI JAC1
TNZ MAB1B
TRA L2P1
MAB1B TRA MAB1
* ROUTINE NINE - ADAPT I/O SELF TEST
* PART ONE - TEST OUTPUT REGISTERS
JAC1 CLA ZERO
STO 776
CIO 066 RESET COMPARE LATCH
CLA =O777777776
CIO 000 SET INT INHIBITS
CLA =O000152204 RESET
CIO 623
CLA =O00002
CIO 613
CLA =O000000040
CIO 030 RST INT 5 LATCH
CIO 004 RST INT 5 INHIBIT
CIO 110 RST MAIN INT LATCH
CLA K77 INHIBIT ACCEL. SUBTRACTS
CIO 126
* LOAD ALL OUTPUT REGISTERS
CIO 006 SSFB
CIO 012 RCA GC DATA
CIO 026 DIS REG
CIO 032 NASA DISCRETES
CIO 136 LOAD ACCEL. DELAY LINES
CIO 142 LOAD ACCEL. DELAY LINES
CIO 146 LOAD ACCEL. DELAY LINES
CIO 046 INT REG
CIO 052 OPTISYN REG
CIO 056 COD SHIFT REG
PIO 777 ADDRESS REG
CLA LC8
TMI JAF1
CLA =O777777776
CIO 022 LOAD DIN REG
CIO 036
CIO 042
* TEST GC DATA REGISTER FOR ONES
JAF1 STO 777
CLA 777 LOCN OF FAILED TEST
STO V4
CLA ZERO
CIO 061 RD GC DATA
XOR =O777760000
TNZ JAJ5
* TEST CR FOR COMPLEMENT OF GC
JAG1 STO 777
CLA 777
STO V4
CIO 065 RD CR DATA
TNZ JAJ5
# PAGE 110, SEQUENCE 53890-54450
* GC REG ALTERNATE PATTERNS
JAH1 STO 777
CLA 777
STO V4
CLA =O525240000
CIO 012 LOAD GC DATA
CLA ZERO
CIO 061
XOR =O525240000
TNZ JAJ5
* CHECK CR DATA FOR COMPLEMENT PATTERN
JAJ1 STO 777
CLA 777
STO V4
CIO 065
XOR =O252520000
TNZ JAJ5
JAK1 STO 777
CLA 777
STO V4
CLA =O252520000
CIO 012
CLA ZERO
CIO 061
XOR =O252520000
TNZ JAJ5
* TEST COMPARE LATCH
JAA2 STO 776
CLA ZERO
STO V4
CLA =O400000000
CIO 066 ENABLE COMPARE
CLA HJAD2
HJAD2 HPC JAD2
STO 404 INT 5 WILL HOP TO NEXT TEST
* TEST COMPARE WITH ACC BIT =1, GC BIT =0
JAC2 STO 776
CLA =O652520000
CIO 061
JAC2A TRA JAJ5
* TEST COMPARE WITH ACC BIT =0, GC BIT =1
JAD2 STO 776
CIO 030 RST INT 5
CIO 110 RST MAIN INT LATCH
* CHECK HOP SAVE AFTER INT 5
CLA 776
XOR HJAC2A
HJAC2A HPC JAC2A
TNZ JAJ5
STO 776
CLA HJAF2
STO 404
HJAF2 HPC JAF2
CLA =O212520000
CIO 061
TRA JAJ5
JAF2 CLA HJAJ5
# PAGE 111, SEQUENCE 54460-55020
STO 404
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA ZERO
CIO 006
CIO 026
CIO 032
CIO 046
CIO 052
CIO 056
CLA LC8
TMI JWB1
CLA ZERO
CIO 022
CIO 036 DDAS REG
CIO 042 EM REG
* CHECK COMPARE LATCH WITH ENABLE COMPARE RESET
JWB1 STO 776
CLA =O253500000
CIO 066 DISABLE COMPARE
CIO 061 READ GC
* NO INT 5 SHOULD OCCUR
* PIC GRP 5 WITH TRS NOT EQUAL TO ACCUM
JWD1 STO 776
CLA =O002000002
STO 773
CLA =O000000100
PIO 773
* NO INT 5 SHOULD OCCUR
* CHECK COMPARE WITH PIO GRP 5
* CORRECT DATA
JWF1 STO 776
CLA K77
CIO 066
CLA =O002000002
PIO 773
* NO INT 5 SHOULD OCCUR
* INCORRECT DATA WITH PIO GRP 5
JWH1 STO 776
CLA HJWK1
HJWK1 HPC JWK1
STO 404
CLA ZERO
PIO 773
* INT 5 SHOULD OCCUR HERE
TRA JAJ5
JWK1 CIO 030 RESET INT 5
CIO 110
JWB3 STO 776
CLA HJWE3
HJWE3 HPC JWE3
STO 404
CLA =O002000000
STO 773
CLA =O002000002
PIO 773
* INT 5 SHOULD OCCUR HERE
# PAGE 112, SEQUENCE 55030-55590
TRA JAJ5
JWE3 CLA HJAJ5
STO 404
CIO 030
CIO 110
* TEST COMPARE WITH CORRECT ACCUMULATOR
JAG2 STO 776
CLA =O252520000
CIO 061
* TEST SSFB REG FOR ZERO
JAH2 STO 777
CLA 777
STO V4
CLA ZERO
CIO 055
* TEST CR REG FOR COMPLIMENT OF GC
JAJ2 STO 777
CLA 777
STO V4
CLA =O525240000
CIO 065
* TEST DISCRETE INPUT SPARES (DIS) FOR ZERO
JAK2 STO 777
CLA 777
STO V4
CLA ZERO
CIO 075
* TEST NASA DISCRETES (NA DIS) FOR ZERO
JAC3 STO 777
CLA 777
STO V4
CLA ZERO
CIO 101
CLA LC8
TMI JAG3
* TEST CIU REG FOR ZERO
JAD3 STO 777
CLA 777
STO V4
CLA ZERO
CIO 105
* TEST INT 1 NOT SET BY CIU 4,5,6 VIA INTCV
ADD ZERO
HOP H9P3
STO 777
CLA 777
STO V4
CIO 154
TNZ JAJ5
ADD ZERO
* TEST EM REG FOR ZERO
JAE3 STO 777
CLA 777
STO V4
CLA ZERO
CIO 111
* TEST DISCRETE INPUTS (DIN REG) FOR ZERO
# PAGE 113, SEQUENCE 55600-56160
JAF3 STO 777
CLA 777
STO V4
CLA ZERO
CIO 071
* TEST OPTISYN REG FOR ZERO
JAG3 STO 777
CLA 777
STO V4
CLA ZERO
CIO 121
* TEST INT SIGNAL REG FOR ZERO
JAH3 STO 777
CLA 777
STO V4
CLA ZERO
CIO 115
* TEST COD SHIFT REGISTER FOR ZERO
JAJ3 STO 777
CLA 777
STO V4
CLA ZERO
CIO 131 TE3A
CIO 141 TE38
TRA JAK3
* LOAD ALL OUTPUT REGISTERS EXCEPT CR ALL ONES
ORG 1,,1,10,1,10,
JAK3 CLA ZERO
STO V4
CLA =O777777776
CIO 012
CIO 026
CIO 032
CIO 046
CIO 052
CIO 056
CIO 006
CLA LC8
TMI JAC4
CLA =O777777776
CIO 022
CIO 036
CIO 042
* TEST CR REG
JAC4 STO 776
CLA =O002520000
CIO 016
CIO 065
JAD4 STO 776
CLA =O001240000
CIO 016
CIO 065
JAE4 STO 776
CLA =O777760000
CIO 016
CIO 065
* TEST GC FOR COMPLEMENT OF CR
# PAGE 114, SEQUENCE 56170-56730
JAF4 STO 776
CLA ZERO
CIO 061
* TEST SSFB REGISTER
JAG4 STO 776
CLA =O002520000
CIO 006
CIO 055
JAH4 STO 776
CLA =O001250000
CIO 006
CIO 055
JAJ4 STO 776
CLA =O003770000
CIO 006
CIO 055
* TEST DIS REGISTER
JAK4 STO 776
CLA =O524000000
CIO 026
CIO 075
JAC5 STO 776
CLA =O252000000
CIO 026
CIO 075
JAD5 STO 776
CLA =O776000000
CIO 026
CIO 075
* TEST NA DIS REGISTER
JAE5 STO 776
CLA =O000000524
CIO 032
CIO 101
JAF5 STO 776
CLA =O000000252
CIO 032
CIO 101
JAG5 STO 776
CLA =O000000776
CIO 032
CIO 101
CLA LC8
TMI JBA2
TRA JBA1
JAJ5 STO 777
JAJ5A STO TEMP
CLA 777
STO VAR2
CLA 776
STO VAR1
JAJ5B CLA =O000000400 SET LTE ERROR LAMP
CIO 603 RESET ALL INT LATCHES
HOP H9P3
CLA TEMP
# PAGE 115, SEQUENCE 56740-57300
HOP H95P7
* TEST CIU REGISTER
JBA1 STO 776
CLA =O525000000
CIO 036
CIO 105
JBB1 STO 776
CLA =O252400000
CIO 036
CIO 105
JBC1 STO 776
CLA =O777400000
CIO 036
CIO 105
* TEST INT 1 SET BY CIU VIA INTCV
ADD ZERO
STO 776
CIO 154
AND =O400000000
TNZ *+2
TRA JAJ5
CIO 010 RESET INT 1
CIO 110
* TEST EM REGISTER
JBD1 STO 776
CLA =O525250000
CIO 042
CIO 111
JBE1 STO 776
CLA =O252524000
CIO 042
CIO 111
JBF1 STO 776
CLA =O777774000
CIO 042
CIO 111
TRA JBG1
* TEST DIN REGISTER
ORG 1,,1,210,1,10,
JBG1 CLA =O252525252
STO 776
* CAL POINT NR 25
CIO 022
CIO 071
JBH1 STO 776
CLA =O525252524
CIO 022
CIO 071
* TEST OPTISYN REGISTER
JBA2 STO 776
CLA =O000012524
CIO 052
CIO 121
JBB2 STO 776
CLA =O000005252
CIO 052
CIO 121
# PAGE 116, SEQUENCE 57310-57870
JBC2 STO 776
CLA =O000017776
CIO 052
CIO 121
* TEST INT SIGNAL REGISTER
JBD2 STO 776
CLA =O125200000
CIO 046
CIO 115
JBE2 STO 776
CLA =O052500000
CIO 046
CIO 115
JBF2 STO 776
CLA =O177700000
CIO 046
CIO 115
* LOAD AND TEST GC REG ALL ONES
JBG2 STO 776
CLA =O777760000
CIO 012
CIO 061
* TEST COD REGISTER
JBH2 STO 776
CLA =O252505252
CIO 056
CIO 131
CIO 141
JBJ2 STO 776
CIO 062 SET COD ENABLE TE2A,B
CLA =O125202524
CIO 056
CIO 131
CIO 141
JBK2 STO 776
CLA =O377707776
CIO 056
CIO 131
CIO 141
CLA =O000000004 RESET COD ENABLE TE2A,B
CIO 623
CLA LC8
TMI JEC1A CHL SWITCHING IN PROGRESS
TRA JBM2
JEC1A TRA JEC1
ORG 1,6,,70,1,10,
* TEST DIN REG FOR ZERO
JBM2 CLA ZERO
STO 776
CIO 022
CIO 071
* CHECK DA INPUTS AND MULTIPLEXER
JBA3 STO 776
CLA =O525252524
CIO 022 LOAD DIN REG
CIO 071 DIN REG
JBB3 STO 776
# PAGE 117, SEQUENCE 57880-58440
CLA =O252525252
CIO 005 GC A DATA IN
JBC3 STO 776
CLA =O525250000
CIO 011 GC B DATA IN
JBD3 STO 776
CLA ZERO
CIO 015 ORBITAL CHECKOUT
JBE3 STO 776
CLA =O525250000
CIO 021 DOR IN
JBF3 STO 776
CLA =O252520000
CIO 031 SSR IN
JBG3 STO 776
CLA =O525252524
CIO 035 TEL DATA A
JBH3 STO 776
CLA =O252520000
CIO 041 TEL DATA B
JBB4 STO 776
CLA =O525250000
CIO 045 DDAS (CIU) DATA IN
JBC4 STO 776
CLA =O252525252
CIO 051 NA SIM LAB IN
* LOAD DIN REG
JBG4 STO 776
CLA =O252525252
CIO 022
CIO 071 READ
JBB5 STO 776
CLA =O525252524
CIO 005 GC A
JBC5 STO 776
CLA =O252520000
CIO 011 GC B
JBD5 STO 776
CLA =O000000002
CIO 015 OCV
JBE5 STO 776
CLA =O252500000
CIO 021 DOR
JBF5 STO 776
CLA =O525250000
CIO 031 SSR
JBG5 STO 776
CLA =O252525252
CIO 035 TEL A
JBH5 STO 776
CLA =O125250000
CIO 041 TEL B
JCB1 STO 776
CLA =O252520000
CIO 045 DDAS IN
JCC1 STO 776
CLA =O525252524
# PAGE 118, SEQUENCE 58450-59010
CIO 051 NA SIM
* LOAD DIN REG
JCH1 STO 776
CLA =O631463146
CIO 022
CIO 071 DIN
JCB2 STO 776
CLA =O714631462
CIO 005 GC A
JCC2 STO 776
CLA =O746310000
CIO 011 GC B
JCD2 STO 776
CLA ZERO
CIO 015 OCV
JCE2 STO 776
CLA =O171440000
CIO 021 DOR
JCF2 STO 776
CLA =O474630000
CIO 031 SSR
JCG2 STO 776
CLA =O636314630
CIO 035 TEL A
JCH2 STO 776
CLA =O317140000
CIO 041 TEL B
JCJ2 STO 776
CLA =O147460000
CIO 045 DDAS
JCK2 STO 776
CLA =O363146314
CIO 051 NA SIM
* LOAD DIN REGISTER
JCB4 STO 776
CLA =O741703606
CIO 022
CIO 071 DIN
JCE4 STO 776
CLA =O760741702
CIO 005 GC A
JCF4 STO 776
CLA =O770360000
CIO 011 GC B
JCG4 STO 776
CLA ZERO
CIO 015 OCV
JCH4 STO 776
CLA =O176050000
CIO 021 DOR
JCJ4 STO 776
CLA =O077030000
CIO 031 SSR
JCB5 STO 776
CLA =O037417036
CIO 035 TEL A
JCC5 STO 776
# PAGE 119, SEQUENCE 59020-59580
CLA =O01760000
CIO 041 TEL B
JCD5 STO 776
CLA =O607700000
CIO 045 DDAS
JCE5 STO 776
CLA =O374170360
CIO 051 NA SIM
TRA JDB1
ORG 1,1,0,12,1,10,
* LOAD DIN REGISTER
JDB1 CLA =O776003770
STO 776
CIO 022
CIO 071
JDE1 STO 776
CLA =O377001774
CIO 005 GC A
JDF1 STO 776
CLA =O177400000
CIO 011 GC B
JDG1 STO 776
CLA =O000000002
CIO 015 OCV
JDH1 STO 776
CLA =O637700000
CIO 021 DOR
JDJ1 STO 776
CLA =O717740000
CIO 031 SSR
JDB2 STO 776
CLA =O747760036
CIO 035 TEL A
JDC2 STO 776
CLA =O363770000
CIO 041 TEL B
JDD2 STO 776
CLA =O771770000
CIO 045 DDAS
JDE2 STO 776
CLA =O477600376
CIO 051 NA SIM
* LOAD DIN REGISTER
JDB3 STO 776
CLA =O777774000
CIO 022
CIO 071
JDE3 STO 776
CLA =O377776000
CIO 005 GC A
JDF3 STO 776
CLA =O177770000
CIO 011 GC B
JDG3 STO 776
CLA ZERO
CIO 015 OCV
JDH3 STO 776
# PAGE 120, SEQUENCE 59590-60150
CLA =O037750000
CIO 021 DOR
JDJ3 STO 776
CLA =O017770000
CIO 031 SSR
JDB4 STO 776
CLA =O007777740
CIO 035 TEL A
JDC4 STO 776
CLA =O003770000
CIO 041 TEL B
JDD4 STO 776
CLA =O001770000
CIO 045 DDAS
JDE4 STO 776
CLA =O077777400
CIO 051 NA SIM
* TEST PIO ADDRESS REGISTER AND MPLXR GATES
JEB1 CLA =O777777776
CIO 022 LOAD DIN REG
CIO 071 READ DIN REG
* TEST PIO ADDRESS REGISTER
JEC1 STO 776
PIO 000
CLA ZERO
CIO 125 READ ADDRESS REG
JEE1 STO 776
PIO 776
CLA =O000001774
CIO 125
JEG1 STO 776
PIO 525
CLA =O000001252
CIO 125
JEJ1 STO 776
PIO 252
CLA =O000000524
CIO 125
* TEST A13 AND LDATAV INTERFACE
* DISABLE COMPARE LATCH
JEA2 CLA LC8
TMI JEB4
JEB2 CLA ZERO
CIO 066
JEC2 STO 776
CLA =O525252524
PIO 137 LOAD EM REG
CIO 111 READ EM REG
XOR =O525200000
TNZ JEJ5
JEE2 STO 776
CLA =O252525252
PIO 137
CIO 111
XOR =O252500000
TNZ JEJ5
JEG2 STO 776
# PAGE 121, SEQUENCE 60160-60720
CLA =O036077776
PIO 137
CIO 111
XOR =O036000000
TNZ JEJ5
JEB3 STO 776
CLA =O741777776
PIO 137
CIO 111
XOR =O741700000
TNZ JEJ5
JED3 STO 776
CLA =O770077776
PIO 137
CIO 111
XOR =O770000000
TNZ JEJ5
JEF3 STO 776
CLA =O007777776
PIO 137
CIO 111
XOR =O007700000
TNZ JEJ5
JEH3 CLA =O777777776
CIO 042 LOAD EM REG
* TEST TRS AND DATAVD INPUT TO MPLXR
JEB4 CIO 066 ENABLE COMPARE
JEC4 STO 776
CLA =O525252524
STO 403
PIO 403 ACC AND INPUT COMPARE
JED4 STO 776
CLA =O252525252
STO 403
PIO 403
JEE4 STO 776
CLA =O631463146
STO 403
PIO 403
JEF4 STO 776
CLA =O146314630
STO 403
PIO 403
JEG4 STO 776
CLA =O741703606
STO 403
PIO 403
JEH4 STO 776
CLA =O036074170
STO 403
PIO 403
JEB5 STO 776
CLA =O776003770
STO 403
PIO 403
JEC5 STO 776
CLA =O001774006
# PAGE 122, SEQUENCE 60730-61290
STO 403
PIO 403
JED5 STO 776
CLA =O777774000
STO 403
PIO 403
JEE6 STO 776
CLA =O000003776
STO 403
PIO 403
CLA ZERO
STO 403
CIO 032 CLEAR NA DIS
CLA LC8
TMI JFB1
CLA ZERO
CIO 036 CLEAR DDAS (CIU)
TRA JFB1
JEJ5 STO 777
TRA JAJ5A
* TEST PIO DECODING AND INTERRUPTS
ORG 1,1,1,12,1,10,
JFB1 HOP H9P3 RESET ALL INT LATCHES
CLA ZERO
CIO 066 DISABLE COMPARE
* INHIBIT ALL INTERRUPTS
CLA =O777777776
CIO 000
CLA LC8
TMI JJB1A
TRA *+2
JJB1A TRA JJB1
STO 776
CIO 154
TNZ JEJ5
* CHECK PIO GROUP 1 OR 3 SET INT 6
JFE1 STO 776
PIO 010 GROUP 1
ADD ZERO
CIO 154 READ INTERRUPT REG.
XOR =O010000000
TNZ JEJ5
JFG1 STO 776
CIO 034 RST INT 6
PIO 001 GROUP 3
ADD ZERO
CIO 154
XOR =O010000000
TNZ JEJ5
JFJ1 STO 776
CIO 034 RST INT 6
PIO 006 GRP 2
PIO 277
CIO 000
ADD ZERO
CIO 154
TNZ JEJ5
# PAGE 123, SEQUENCE 61300-61860
* CHECK PIO LOAD SW SEL REG SETS INT 2
JFB2 STO 776
PIO 036
ADD ZERO
CIO 154
XOR =O20000000
TNZ JEJ5
* PERFORM DIODE TESTS
JFD2 STO 776
CIO 014 RST INT 2
PIO 037
PIO 034
PIO 032
PIO 026
PIO 016
PIO 076
PIO 136
CLA LC8
TMI *+3
CLA ZERO
CIO 036
CIO 034 RESET INT 6
CIO 154
TNZ JEJ5
* CHECK PIO READ INTERRUPT REGISTER SET INT 8
JFF2 STO 776
PIO 137
ADD ZERO
CIO 154
XOR =O002000000
TNZ JEJ5
* PERFORM NEGATIVE TESTS
JFH2 STO 776
CIO 044 RST INT 8
PIO 135
PIO 133
PIO 127
PIO 117
PIO 177
CIO 137
CIO 034 RESET INT 6
CIO 154
TNZ JEJ5
* CHECK PIO READ FINE GIMBAL SETS INT 9
JFB3 STO 776
PIO 223
ADD ZERO
CIO 154
XOR =O001000000
TNZ JEJ5
JFD3 STO 776
CIO 050 RST INT 9
PIO 227
ADD ZERO
CIO 154
XOR =O001000000
TNZ JEJ5
# PAGE 124, SEQUENCE 61870-62430
JFF3 STO 776
CIO 050 RST INT 9
PIO 353
ADD ZERO
CIO 154
XOR =O001000000
TNZ JEJ5
JFH3 STO 776
CIO 050 RST INT 9
PIO 363
ADD ZERO
CIO 154
XOR =O001000000
TNZ JEJ5
* PERFORM DIODE TESTS
JFB4 STO 776
CIO 050 RST INT 9
PIO 222
PIO 221
CIO 223
PIO 303
PIO 313
PIO 317
PIO 253
PIO 263
PIO 373
PIO 357
PIO 323
PIO 367
PIO 203
PIO 213
CIO 034 RESET INT 6
CIO 154
TNZ JEJ5
* CHECK PIO READ COARSE GIMBAL SETS INT 10
JFF4 STO 776
PIO 243
ADD ZERO
CIO 154
XOR =O000400000
TNZ JEJ5
JFH4 STO 776
CIO 054 RST INT 10
PIO 343
ADD ZERO
CIO 154
XOR =O000400000
TNZ JEJ5
JFB5 STO 776
CIO 054 RST INT 10
PIO 233
ADD ZERO
CIO 154
XOR =O000400000
TNZ JEJ5
JFD5 STO 776
CIO 054 RST INT 10
# PAGE 125, SEQUENCE 62440-63000
PIO 333
ADD ZERO
CIO 154
XOR =O000400000
TNZ JEJ5
* PERFORM DIODE TESTS
JFF5 STO 776
CIO 054 RST INT 10
PIO 247
PIO 347
PIO 237
PIO 273
PIO 340
PIO 337
PIO 043
CIO 034 RESET INT 6
CIO 154
TNZ JEJ5
* CHECK PIO READ SW SEL REG SETS INT 11
JGB1 STO 776
PIO 077
ADD ZERO
CIO 154
XOR =O000200000
TNZ JEJ5
* CHECK PIO READ DIN REG SETS INT 12
JGD1 STO 776
CIO 060 RST INT 11
PIO 057
ADD ZERO
CIO 154
XOR =O000100000
TNZ JEJ5
* CHECK PIO READ EM REG SETS INT 13
JGF1 STO 776
CIO 064 RST INT 12
PIO 023
ADD ZERO
CIO 154
XOR =O000040000
TNZ JEJ5
* CHECK PIO READ TEL SCANNER SETS INT 14
JGH1 STO 776
CIO 070 RST INT 13
CIO 220 READ B SWITCHES
AND =O100000000 B2
TNZ JGB2
PIO 067
ADD ZERO
CIO 154
XOR =O000020000
TNZ JEJ5
* PERFORM DIODE TESTS
JGB2 STO 776
# PAGE 126, SEQUENCE 63010-63570
CIO 074 RST INT 14
PIO 073
PIO 075 SETS INT 6
PIO 157
PIO 257
PIO 047
PIO 017
PIO 053
PIO 056
PIO 123
PIO 003
PIO 063
PIO 033
PIO 021 SETS INT 6
PIO 022
PIO 027
PIO 167
PIO 267
PIO 047
PIO 027
PIO 066
PIO 065 SET INT 6
PIO 063
CIO 034 RST INT 6
CIO 023
ADD ZERO
CIO 154
TNZ JEJ5
TRA JHB1
ORG 1,2,0,14,1,10,
* CHECK NASA INT 1 AND 2, NDI 1-6
JHB1 CLA ZERO
STO 776
CIO 032 LOAD NA DIS REG
JHC1 STO 777
CLA 777
STO VAR4
ADD ZERO
CIO 154
TNZ JHJ5
JHD1 STO 777
CLA 777
STO V4
CIO 214
AND =O000001760
TNZ JHJ5
JHE1 STO 776
CLA =O000000524
CIO 032
JHF1 STO 777
CLA 777
STO V4
ADD ZERO
CIO 154
XOR =O040000000 INT 4
TNZ JHJ5
# PAGE 127, SEQUENCE 63580-64140
JHG1 STO 777
CLA 777
STO V4
CIO 214
AND =O000001760
XOR =O000001240 DI 2,4,6
TNZ JHJ5
JHB2 STO 776
CLA ZERO
CIO 032
CIO 024 RST 4
CLA =O000000252
CIO 032
JHC2 STO 777
CLA 777
STO V4
ADD ZERO
CIO 154
XOR =O100000000 INT 3
TNZ JHJ5
JHD2 STO 777
CLA 777
STO V4
CIO 214
AND =O000001760
XOR =O000000520 DI 1,3,5
TNZ JHJ5
JHE2 STO 776
CLA ZERO
CIO 032
CIO 020 RESET INT 3
CLA =O000000630
CIO 032
JHF2 STO 777
CLA 777
STO V4
ADD ZERO
CIO 154
TNZ JHJ5
JHG2 STO 777
CLA 777
STO V4
CIO 214
AND =O000001760
XOR =O000001460 DI 1,2,5,6
TNZ JHJ5
JHB3 STO 776
CLA =O000000146
CIO 032
JHC3 STO 777
CLA 777
STO V4
ADD ZERO
CIO 154
XOR =O140000000 INT 3,4
TNZ JHJ5
JHD3 STO 777
# PAGE 128, SEQUENCE 64150-64710
CLA 777
STO V4
CIO 214
AND =O000001760
XOR =O000000300 DI 3,4
TNZ JHJ5
JHE3 CLA ZERO
CIO 032
STO V4
CIO 020
CIO 024
CIO 110
TRA JJB1
JHJ5 STO 777
TRA JAJ5A
* CHECK OF TSYNC/GCSYNC CIRCUITRY
* CORRECT OPERATION MONITORED BY OSCILLOSCOPE ONLY
JJB1 CLA =O677777776
CIO 072 SET 1 TSYNC PULSE
CLA =O000000014
SUB K1
TNZ *-1
CLA =O277777776
CIO 072 ATTEMPT SOLID TSYNC RESET - DIODE CHK
CLA =O000000014
SUB K1
TNZ *-1
CLA =O677777776
CIO 072 SELECT TSYNC MODE
CIO 102 SET 240 PPS ON TSYNC
CLA =O000000014
SUB K1
TNZ *-1
CLA =O277777776
CIO 072 ATTEMPT EARLY RESET -DIODE CHK
CLA =O000000334
SUB K1
TNZ *-1 COUNT 220 DEC WORD TIMES
CLA =O677777776
CIO 072 RESET 240 PPS ON TSYNC
CLA =O000000014
SUB K1
TNZ *-1
CLA =O777777776
CIO 072 SET SOLID TSYNC
CLA =O000000004
JJB3 CIO 076 ATTEMPT SOLID TSYNC RESET - DIODE CHK
SUB K1
TNZ *-1 COUNT 6 DEC WORD TIMES
CLA =O277777776
CIO 072 RESET SOLID TSYNC
ADD ZERO
CLA =O537777776
CIO 076 DIODE CHK
ADD ZERO
ADD ZERO
# PAGE 129, SEQUENCE 64720-65280
* TO LOOP ON TSYNC PLACE B5 SWITCH UP
CIO 220
AND =O01
TNZ JJB1
JKB1 CLA =O737777776
CIO 076 SET 1 GCSYNC PULSE
CLA =O000000014
SUB K1
TNZ *-1
CLA =O537777776
CIO 076 ATTEMPT SOLID GCSYNC RESET -DIODE CHK
CLA =O000000014
SUB K1
TNZ *-1
CLA =O737777776
CIO 076 SELECT GCSYNCE MODE
CIO 102 SET 240 PPS ON GCSYNC
CLA =O000000014
SUB K1
TNZ *-1
CLA =O537777776
CIO 076 ATTEMPT EARLY RESET - DIODE CHK
CLA =O000000334
SUB K1
TNZ *-1 COUNT 220 DECIMAL WORD TIMES
CLA =O737777776
CIO 076 RESET 240 PPS ON GCSYNC
CLA =O000000014
SUB K1
TNZ *-1
CLA =O777777776
CIO 076 SET SOLID GCSYNC
JKB3 CLA =O000000004
CIO 072 ATTEMPT SOLID GCSYNC RESET -DIODE CHK
SUB K1
TNZ *-1 COUNT 6 DEC WORD TIMES
CLA =O537777776
CIO 076 RESET SOLID GCSYNC
ADD ZERO
CLA =O277777776
CIO 072 DIODE CHK
* TO LOOP ON GCSYNC PLACE B6 SWITCH UP
CIO 220
AND =O004
TNZ JKB1
TRA JLB1
ORG 1,2,1,14,1,11,
* CHECK ACCELEROMETER SIMULATOR
* CHECK PLUS STEP FROM Q+R=0
JLB1 CLA HJMB1
STO 776
HJMB1 HPC JMB1
STO V2
CLA =O777777776
CIO 066 ENABLE COMPARE
CIO 132 SET ACCEL SIGNS PLUS
# PAGE 130, SEQUENCE 65290-65850
CIO 126 SET SUBTRACT INHIBIT
CLA HJAJ5
STO 404
CLA ZERO
CIO 052 LOAD OPT REG Q+R=0
CIO 121 CHECK OPT REG LOAD
CLA =O001500016
CIO 136 LOAD X CHAN CTR
CIO 142 LOAD Y CHAN CTR
CLA =O002540000
CIO 146 LOAD Z CHAN CTR
CIO 126 RESET SUBTRACT INHIBIT
CLA =O000000040 RST INT 5 INHIBIT
CIO 004
ADD ZERO
CLA HJLB2
HJLB2 HPC JLB2
STO 404
CLA ZERO
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JLK1 TRA JLJ5
JLB2 STO 777
STO TEMP
CLA BB
CIO 126 INH X CHAN SUBTRACT
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJLK1 CORRECT ENTRY LOCATION
HJLK1 HPC JLK1
TNZ JLB3
CLA TEMP
XOR =O000012000 X CHAN STEP FROM 00 TO 10
TNZ JLJ5
CLA HJLB4
HJLB4 HPC JLB4
STO 404
CLA =O00001200
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JLJ2 TRA JLJ5
JLB4 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJLJ2 CORRECT ENTRY LOCATION
HJLJ2 HPC JLJ2
TNZ JLB3
CLA TEMP
XOR =O000012500 Y CHAN STEP FROM 00 TO 10
TNZ JLJ5
CLA HJLB5
HJLB5 HPC JLB5
# PAGE 131, SEQUENCE 65860-66520
STO 404
CLA =O000012500
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JLJ4 TRA JLJ5
JLB5 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJLJ4 CORRECT ENTRY LOCATION
HJLJ4 HPC JLJ4
TNZ JLB3
CLA TEMP
XOR =O000012524 Z CHAN STEP FROM 00 TO 10
TNZ JLJ5
CLA K77
CIO 126 SET SUBTRACT INHIBIT
TRA JMB1
JLJ5 STO TEMP
JLB3 HOP HJAJ5B
* CHECK PLUS STEP FROM Q=1,R=0
JMB1 STO 776
CLA HJNB1
HJNB1 HPC JNB1
STO V2
CLA HJAJ5
STO 404
CLA =O000012524
CIO 052 LOAD OPT REG Q=1,R=0
CIO 121 CHECK OPT REG LOAD
CLA =O000340064
CIO 136 LOAD X CHAN CTR
CIO 142 LOAD Y CHAN CTR
CLA =O002540000
CIO 146 LOAD Z CHAN CTR
CIO 126 RESET SUBTRACT INHIBIT
ADD ZERO
ADD ZERO
ADD ZERO
CLA HJMB2
HJMB2 HPC JMB2
STO 404
CLA =O000012524
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JMK1 TRA JLJ5
JMB2 STO 777
STO TEMP
CLA =O000000004
CIO 126 INH Y CHAN SUBTRACT
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJMK1 CORRECT ENTRY LOCATION
# PAGE 132, SEQUENCE 66430-66990
HJMK1 HPC JMK1
TNZ JLB3
CLA TEMP
XOR =O000012764 Y CHAN STEP FROM 10 TO 11
TNZ JLJ5
CLA HJMB3
HJMB3 HPC JMB3
STO 404
CLA =O000012764
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JMJ2 TRA JLJ5
JMB3 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJMJ2 CORRECT ENTRY LOCATION
HJMJ2 HPC JMJ2
TNZ JLB3
CLA TEMP
XOR =O000017764 X CHAN STEP FROM 10 TO 11
TNZ JLJ5
CLA HJMB4
HJMB4 HPC JMB4
STO 404
CLA =O000017764
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JMJ3 TRA JLJ5
JMB4 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJMJ3 CORRECT ENTRY LOCATION
HJMJ3 HPC JMJ3
TNZ JLB3
CLA TEMP
XOR =O000017776 Z CHAN STEP FROM 10 TO 11
TNZ JLJ5
CLA K77
CIO 126 SET SUBTRACT INHIBIT
* CHECK MINUS STEP FROM Q+R=1
JNB1 STO 776
CLA HJPB1
HJPB1 HPC JPB1
STO V2
CLA HJAJ5
STO 404
CLA ZERO
CIO 132 SET ACCEL SIGNS MINUS
CLA =O000017776
CIO 052 LOAD OPT REG Q+R=1
CIO 121 CHECK OPT REG LOAD
# PAGE 133, SEQUENCE 67000-67560
CLA =O000340000
CIO 146 LOAD Z CHAN CTR
CLA =O002540064
CIO 142 LOAD Y CHAN CTR
CIO 136 LOAD X CHAN CTR
CLA ZERO
CIO 126 RESET SUBTRACT INHIBIT
ADD ZERO
ADD ZERO
ADD ZERO
CLA HJNB2
HJNB2 HPC JNB2
STO 404
CLA =O000017776
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JNK1 TRA JLJ5
JNB2 STO 777
STO TEMP
CLA K1
CIO 126 INH Z CHAN SUBTRACT
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJNK1 CORRECT ENTRY LOCATION
HJNK1 HPC JNK1
TNZ JLB3
CLA TEMP
XOR =O000017764 Z CHAN STEP FROM 11 TO 10
TNZ JLJ5
CLA HJNB3
HJNB3 HPC JNB3
STO 404
CLA =O000017764
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JNJ2 TRA JLJ5
JNB3 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJNJ2 CORRECT ENTRY LOCATION
HJNJ2 HPC JNJ2
TNZ JLB3
CLA TEMP
XOR =O000012764 X CHAN STEP FROM 11 TO 10
TNZ JLJ5
CLA HJNB4
HJNB4 HPC JNB4
STO 404
CLA =O000012764
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JNJ3 TRA JLJ5
# PAGE 134, SEQUENCE 67570-68130
JNB4 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJNJ3 CORRECT ENTRY LOCATION
HJNJ3 HPC JNJ3
TNZ JLB3
CLA TEMP
XOR =O000012524 Y CHAN STEP FROM 11 TO 10
TNZ JLJ5
CLA K77
CIO 126 SET SUBTRACT INHIBIT
TRA JPB1
ORG 1,3,0,20,1,11,
* CHECK MINUS STEP FROM Q=1,R=0
JPB1 CLA HJQB1
STO 776
HJQB1 HPC JQB1
STO V2
CLA HJAJ5
STO 404
CLA =O000012524
CIO 052 LOAD OPT REG Q=1,R=0
CIO 121 CHECK OPT REG LOAD
CLA =O000340000
CIO 146 LOAD Z CHAN CTR
CLA =O002540064
CIO 142 LOAD Y CHAN CTR
CIO 136 LOAD X CHAN CTR
CLA ZERO
CIO 126 RESET SUBTRACT INHIBIT
ADD ZERO
ADD ZERO
ADD ZERO
CLA HJPB2
HJPB2 HPC JPB2
STO 404
CLA =O000012524
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JPK1 TRA JLJ5
JPB2 STO 777
STO TEMP
CLA K1
CIO 126 INH Z CHAN SUBTRACT
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJPK1 CORRECT ENTRY LOCATION
HJPK1 HPC JPK1
TNZ JPJ5
CLA TEMP
XOR =O000012500 Z CHAN STEP FROM 10 TO 00
TNZ JPJ4
# PAGE 135, SEQUENCE 68140-68700
CLA HJPB3
HJPB3 HPC JPB3
STO 404
CLA =O000012500
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JPJ2 TRA JLJ5
JPB3 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJPJ2 CORRECT ENTRY LOCATION
HJPJ2 HPC JPJ2
TNZ JPJ5
CLA TEMP
XOR =O000000500 X CHAN STEP FROM 10 TO 00
TNZ JPJ4
CLA HJPB4
HJPB4 HPC JPB4
STO 404
CLA =O000000500
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JPJ3 TRA JLJ5
JPB4 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJPJ3 CORRECT ENTRY LOCATION
HJPJ3 HPC JPJ3
TNZ JPJ5
CLA TEMP
TNZ JPJ4 Y CHAN STEP FROM 10 TO 00
CLA K77
CIO 126 SET SUBTRACT INHIBIT
* CHECK PLUS STEP FROM Q+R=1
JQB1 STO 776
CLA HJRB1
HJRB1 HPC JRB1
STO V2
CLA HJAJ5
STO 404
CLA =O777777776
CIO 132 SET ACCEL SIGNS PLUS
CLA =O000017776
CIO 052 LOAD OPT REG Q+R=1
CIO 121 CHECK OPT REG LOAD
CLA =O001500016
CIO 136 LOAD X CHAN CTR
CIO 146 LOAD Z CHAN CTR
CLA =O002540000
CIO 142 LOAD Y CHAN CTR
CIO 126 RESET SUBTRACT INHIBIT
# PAGE 136, SEQUENCE 68710-69270
ADD ZERO
ADD ZERO
ADD ZERO
CLA HJQB2
HJQB2 HPC JQB2
STO 404
CLA =O000017776
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JQK1 TRA JLJ5
JQB2 STO 777
STO TEMP
CLA BB
CIO 126 INH X CHAN SUBTRACT
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJQK1 CORRECT ENTRY LOCATION
HJQK1 HPC JQK1
TNZ JPJ5
CLA TEMP
XOR =O000005776 X CHAN STEP FROM 11 TO 100
TNZ JPJ4
CLA HJQB3
HJQB3 HPC JQB3
STO 404
CLA =O000005776
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JQJ2 TRA JLJ5
JQB3 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJQJ2 CORRECT ENTRY LOCATION
HJQJ2 HPC JQJ2
TNZ JPJ5
CLA TEMP
XOR =O000005752 Z CHAN STEP FROM 11 TO 01
TNZ JPJ4
CLA HJQB4
HJQB4 HPC JQB4
STO 404
CLA =O000005752
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JQJ3 TRA JLJ5
JQB4 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJQJ3 CORRECT ENTRY LOCATION
# PAGE 137, SEQUENCE 69280-69840
HJQJ3 HPC JQJ3
TNZ JPJ5
CLA TEMP
XOR =O000005252 Y CHAN STEP FROM 11 TO 01
TNZ JPJ4
CLA K77
CIO 126 SET SUBTRACT INHIBIT
* CHECK MINUS STEP FROM Q=0,R=1
JRB1 STO 776
CLA HJSB1
HJSB1 HPC JSB1
STO V2
CLA HJAJ5
STO 404
CLA ZERO
CIO 132 SET ACCEL SIGNS MINUS
CLA =O000005252
CIO 052 LOAD OPT REG Q=0,R=1
CIO 121 CHECK OPT REG LOAD
CLA =O000340126
CIO 142 LOAD Y CHAN CTR
CIO 136 LOAD X CHAN CTR
CLA =O001500000
CIO 146 LOAD Z CHAN CTR
CIO 126 RESET SUBTRACT INHIBIT
ADD ZERO
ADD ZERO
ADD ZERO
CLA HJRB2
HJRB2 HPC JRB2
STO 404
CLA =O000005252
CIO 121 COMPARE
CIO 121 NO COMARE - INT 5
JRK1 TRA JLJ5
JRB2 STO 777
STO TEMP
CLA =O000000004
CIO 126 INH Y CHAN SUBTRACT
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJRK1 CORRECT ENTRY LOCATION
HJRK1 HPC JRK1
TNZ JPJ5
CLA TEMP
XOR =O000005752 Y CHAN STEP FROM 01 TO 11
TNZ JPJ4
CLA HJRB3
HJRB3 HPC JRB3
STO 404
CLA =O000005752
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JRJ2 TRA JLJ5
JRB3 STO 777
# PAGE 138, SEQUENCE 69850-70410
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJRJ2 CORRECT ENTRY LOCATION
HJRJ2 HPC JRJ2
TNZ JPJ5
CLA TEMP
XOR =O000005776 Z CHAN STEP FROM 01 TO 11
TNZ JPJ4
CLA HJRB4
HJRB4 HPC JRB4
STO 404
CLA =O000005776
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JRJ3 TRA JLJ5
JRB4 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJRJ3 CORRECT ENTRY LOCATION
HJRJ3 HPC JRJ3
TNZ JPJ5
CLA TEMP
XOR =O000017776 X CHAN STEP FROM 01 TO 11
TNZ JPJ4
CLA K77
CIO 126 SET SUBTRACT INHIBIT
TRA JSB1
JPJ4 STO TEMP
JPJ5 HOP HJAJ5B
ORG 1,3,1,20,1,11,
* CHECK PLUS STEP FROM Q=0,R=1
JSB1 CLA HJTB1
STO 776
HJTB1 HPC JTB1
STO V2
CLA HJAJ5
STO 404
CLA =O777777776
CIO 132 SET ACCEL SIGNS PLUS
CLA =O000005252
CIO 052 LOAD OPT REG Q=0,R=1
CIO 121 CHECK OPT REG LOAD
CLA =O002540016
CIO 146 LOAD Z CHAN CTR
CIO 136 LOAD X CHAN CTR
CLA =O001500000
CIO 142 LOAD Y CHAN CTR
CIO 126 RESET SUBTRACT INHIBIT
ADD ZERO
ADD ZERO
ADD ZERO
# PAGE 139, SEQUENCE 70420-70980
CLA HJSB2
HJSB2 HPC JSB2
STO 404
CLA =O000005252
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JSK1 TRA JLJ5
JSB2 STO 777
STO TEMP
CLA BB
CIO 126 INH X CHAN SUBTRACT
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJSK1 CORRECT ENTRY LOCATION
HJSK1 HPC JSK1
TNZ JPJ5
CLA TEMP
XOR =O000000252 X CHAN STEP FROM 01 TO 00
TNZ JPJ4
CLA HJSB3
HJSB3 HPC JSB3
STO 404
CLA =O000000252
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JSJ2 TRA JLJ5
JSB3 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJSJ2 CORRECT ENTRY LOCATION
HJSJ2 HPC JSJ2
TNZ JPJ5
CLA TEMP
XOR =O000000012 Y CHAN STEP FROM 01 TO 00
TNZ JPJ4
CLA HJSB4
HJSB4 HPC JSB4
STO 404
CLA =O000000012
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JSJ3 TRA JLJ5
JSB4 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJSJ3 CORRECT ENTRY LOCATION
HJSJ3 HPC JSJ3
TNZ JPJ5
CLA TEMP
# PAGE 140, SEQUENCE 70990-71550
TNZ JPJ4 Z CHAN STEP FROM 01 TO 00
CLA K77
CIO 126 SET SUBTRACT INHIBIT
* CHECK MINUS STEP FROM Q+R=0
JTB1 STO 776
CLA HJUB1
STO V2
CLA HJAJ5
STO 404
CLA ZERO
CIO 132 SET ACCEL SIGNS MINUS
CLA ZERO
CIO 052 LOAD OPT REG Q+R=0
CIO 121 CHECK OPT REG LOAD
CLA =O001500126
CIO 142 LOAD Y CHAN CTR
CIO 136 LOAD X CHAN CTR
CLA =O000340000
CIO 146 LOAD Z CHAN CTR
CIO 126 RESET SUBTRACT INHIBIT
ADD ZERO
ADD ZERO
ADD ZERO
CLA HJTB2
HJTB2 HPC JTB2
STO 404
CLA ZERO
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JTK1 TRA JLJ5
JTB2 STO 777
STO TEMP
CLA K1
CIO 126 INH Z CHAN SUBTRACT
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJTK1 CORRECT ENTRY LOCATION
HJTK1 HPC JTK1
TNZ JPJ5
CLA TEMP
XOR =O000000012 Z CHAN STEP FROM 00 TO 01
TNZ JPJ4
CLA HJTB3
HJTB3 HPC JTB3
STO 404
CLA =O000000012
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JTJ2 TRA JLJ5
JTB3 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
# PAGE 141, SEQUENCE 71560-72120
XOR HJTJ2 CORRECT ENTRY LOCATION
HJTJ2 HPC JTJ2
TNZ JPJ5
CLA TEMP
XOR =O000000252 Y CHAN STEP FROM 00 TO 01
TNZ JPJ4
CLA HJTB4
HJTB4 HPC JTB4
STO 404
CLA =O000000252
CIO 121 COMPARE
CIO 121 NO COMPARE - INT 5
JTJ3 TRA JLJ5
JTB4 STO 777
STO TEMP
CIO 030 RESET INT 5
CIO 110 RESET MAIN INT LATCH
CLA 777
STO V4
XOR HJTJ3 CORRECT ENTRY LOCATION
HJTJ3 HPC JTJ3
TNZ JPJ5
CLA TEMP
XOR =O000005252 X CHAN STEP FROM 00 TO 01
TNZ JPJ4
CLA K77
CIO 126 SET SUBTRACT INHIBIT
TRA JUB1
ORG 1,4,0,20,1,11,
* CHECK REGISTER RATE REGEN 1
JUB1 CLA HJUB1
STO 776
HJUB1 HPC JUB1
STO V1
CLA HJVB1A
HJVB1A HPC JVB1
STO V2
CLA HJAJ5
STO 404
CLA =O000000044
CIO 136 LOAD X CHAN CTR
CLA =O000000006
CIO 126 RESET X CHAN SUBTRACT INHIBIT
CLA ZERO
CIO 052 LOAD OPT REG Q+R=0
CIO 121 CHECK OPT REG LOAD
CLA =O001100002
CIO 142 LOAD Y CHAN CTR
CIO 126 RESET Y CHAN SUBTRACT INHIBIT
ADD ZERO
CLA ZERO
CIO 066 RESET COMPARE
CLA =O001100000
CIO 146 LOAD Z CHAN CTR
CIO 126 RESET Z CHAN SUBTRACT INHIBIT
CLA =O000000012
CIO 132 ACCEL SIGNS X=PLUS,Y=MINUS,Z=PLUS
# PAGE 142, SEQUENCE 72130-72690
ADD ZERO
JUG1 STO 777
CLA 777
STO V4
CIO 121
XOR =O000012000 X STEP FROM 00 TO 10
TNZ JUJ2
JUJ1 STO 777
CLA 777
STO V4
CIO 121
XOR =O000012240 Y STEP FROM 00 TO 01
TNZ JUJ2
JUA3 STO 777
CLA 777
STO V4
CIO 121
XOR =O000012264 Z STEP FROM 00 TO 10
TNZ JUJ2
JUC3 STO 777
CLA 777
STO V4
CIO 121
XOR =O000017264 X STEP FROM 10 TO 11
TNZ JUJ2
JUE3 STO 777
CLA 777
STO V4
CIO 121
XOR =O000017764 Y STEP FROM 01 TO 11
TNZ JUJ2
JUG3 STO 777
CLA 777
STO V4
CIO 121
XOR =O000017776 Z STEP FROM 10 TO 11
TNZ JUJ2
JUJ3 STO 777
CLA 777
STO V4
CIO 121
XOR =O000005776 X STEP FROM 11 TO 01
TNZ JUJ2
JUA5 STO 777
CLA 777
STO V4
CIO 121
XOR =O000005536 Y STEP FROM 11 TO 10
TNZ JUJ2
JUC5 STO 777
CLA 777
STO V4
CIO 121
XOR =O000005512 X STEP FROM 11 TO 01
TNZ JUJ2
JUE5 STO 777
CLA 777
# PAGE 143, SEQUENCE 72700-73260
STO V4
CIO 121
XOR =O000000512 X STEP FROM 01 TO 00
TNZ JUJ2
JUG5 STO 777
CLA 777
STO V4
CIO 121
XOR =O000000012 Y STEP FROM 10 TO 00
TNZ JUJ2
JUJ5 STO 777
CLA 777
STO V4
CIO 121
TNZ JUJ2 Z STEP FROM 01 TO 0
CLA K77
CIO 126 SET SUBTRACT INHIBIT
TRA JVB1
JUJ2 TRA JVJ2
ORG 1,4,1,20,1,11,
* CHECK REGISTER RATE REGEN 2
JVB1 CLA HJVB1
STO 776
HJVB1 HPC JVB1
STO V1
CLA HJYB1
HJYB1 HPC JYB1
STO V2
CLA HJAJ5
STO 404
CLA K77
CIO 066 SET COMPARE
CLA =O001100000
CIO 146 LOAD Z CHAN CTR
CLA =O000000014
CIO 126 RESET Z CHAN SUBTRACT INHIBIT
CLA =O000017776
CIO 052 LOAD OPT REG Q+R=1
CIO 121 CHECK OPT REG. LOAD
CLA =O001100010
CIO 142 LOAD Y CHAN CTR
CIO 126 RESET Y CHAN SUBTRACT INHIBIT
CLA ZERO
CIO 066 RESET COMPARE
CLA =O000000044
CIO 136 LOAD X CHAN CTR
CLA ZERO
CIO 126 RESET X CHAN SUBTRACT INHIBIT
CLA =O000000004
CIO 132 ACCEL. SIGNS X=MINUS, Y=PLUS,Z=MINUS
ADD ZERO
JVG1 STO 777
CLA 777
STO V4
CIO 121
XOR =O000017764 Z STEP FROM 11 TO 10
# PAGE 144, SEQUENCE 73270-73830
TNZ JVJ2
JVJ1 STO 777
CLA 777
STO V4
CIO 121
XOR =O000017264 Y STEP FROM 11 TO 01
TNZ JVJ2
JVA3 STO 777
CLA 777
STO V4
CIO 121
XOR =O000012264 X STEP FROM 11 TO 10
TNZ JVJ2
JVC3 STO 777
CLA 777
STO V4
CIO 121
XOR =O000012240 Z STEP FROM 10 TO 00
TNZ JVJ2
JVE3 STO 777
CLA 777
STO V4
CIO 121
XOR =O000012000 Y STEP FROM 01 TO 00
TNZ JVJ2
JVG3 STO 777
CLA 777
STO V4
CIO 121
ADD ZERO
TNZ JVJ2 X STEP FROM 10 TO 00
JVJ3 STO 777
CLA 777
STO V4
CIO 121
XOR =O000000012 Z STEP FROM 00 TO 01
TNZ JVJ2
JVA5 STO 777
CLA 777
STO V4
CIO 121
XOR =O000000512 Y STEP FROM 00 TO 10
TNZ JVJ2
JVC5 STO 777
CLA 777
STO V4
CIO 121
XOR =O000005512 X STEP FROM 00 TO 01
TNZ JVJ2
JVE5 STO 777
CLA 777
STO V4
CIO 121
XOR =O000005536 Z STEP FROM 01 TO 11
TNZ JVJ2
JVG5 STO 777
CLA 777
# PAGE 145, SEQUENCE 73840-74400
STO V4
CIO 121
XOR =O000005776 Y STEP FROM 10 TO 11
TNZ JVJ2
JVJ5 STO 777
CLA 777
STO V4
CIO 121
XOR =O000017776 X STEP FROM 01 TO 11
TNZ JVJ2
CLA ZERO
STO V4
* CHECK LVDA POWER SUPPLY LINES AND A/D CONVERTERS
* SET DA POWER SUPPLY SWITCH TO POSITION 1
K35A OCT 000311120
K35B OCT 000320340
JXC1 CIO 066 DISABLE COMPARE
STO 776
CIO 233 SEL LVDA +28A
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K35A
TMI JYJ5 LESS THAN 27.5
STO 776
CLA K35B
SUB TEMP
TMI JYJ5 GREATER THAN 28.5
JXF1 STO 776
CIO 243 LVDA + 28B
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K35A
TMI JYJ5 LESS THAN 27.5
STO 776
CLA K35B
SUB TEMP
TMI JYJ5 GREATER THAN 28.5
JXJ1 STO 776
CIO 253 LVDA + 28C
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K35A
TMI JYJ5 LESS THAN 27.5
STO 776
CLA K35B
SUB TEMP
TMI JYJ5 GREATER THAN 28.5
JXB2 STO 776
CIO 263 LVDA + 28D
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K35A
TMI JYJ5 LESS THAN 27.5
STO 776
CLA K35B
SUB TEMP
# PAGE 146, SEQUENCE 74410-74840
TMI JYJ5 GREATER THAN 28.5
CIO 220 READ B SWITCHES
AND =O100000000 B2
TNZ JYB1
TRA JYE1
JVJ2 STO TEMP
CLA =O000000400
CIO 603 SET LTE ERROR LAMP
CLA TEMP
HOP H95P7
* SET AND RESET TE1H LATCH
* TE1H UP FOR TWO WORD TIMES
JYB1 STO 776
CLA K77
CIO 000 SET INT INHIBIT
CLA =O000040000
CIO 613
* SHOULD SET INT 14
CLA =O000020000
CIO 623
CIO 154
XOR =O000020000
TNZ JYJ5
CIO 074 RST INT 14
* SET AND RESET DST LATCH
* DST UP FOR ONE WORD TIME
JYE1 CIO 106
CIO 112
* SET AND RESET HLT LATCH
* HLT UP FOR ONE WORD TIME
JYH1 CIO 116
CIO 122
CLA K77
CIO 000 INHIBIT ALL INTERRUPTS
HOP H9P3 RST INT REG
CIO 110
TRA MAB1
JYJ5 STO 777
TRA JAJ5A
# PAGE 147, SEQUENCE 74860-75420
ORG 1,5,0,20,1,11,
MAB1 CLA LCR10
TMI MAC1
TNZ MAB1A
HOP H2P1
MAB1A TRA NAB2
* EXERCISE TELEMETRY POWER SUPPLY SENSE INDICATORS
MAC1 CLA ZERO
STO MCTR
CIO 066
CDS 1,5
CLA MAE1
AND KX8 REMOVE ADDRESS
STO TEMP
CLA KMAE1
AND KX7 KEEP ADDRESS
XOR TEMP
STO MAE1
CDS 1,11
CLA =O000100000 RESET TEL P.S. SENSE
CIO 623
MAD1 CLA =O000040000 RESET INDICATOR
CIO 623
TRA MAH1
MAE1 CLA MDATA
CIO 022 LOAD DIN REG
CLA =O000100000 ENABLE TEL. P.S. SENSE
CIO 613
TRA MAJ1
TRA MAF1
MAJ1 STO 777
CLA =O000025234 DELAY 894 MSEC.
SUB K1
TNZ *-1
HOP 777
MAF1 CLA =O000100000 DIABLE DEL P.S. SENSE
CIO 623
TRA MAH1 DELAY
CLA MCTR
ADD KS1
STO MCTR
SUB =O060000000 =24
TNZ MAG1
TRA JXG1
KMAE1 CLA MDATA
MAG1 CDS 1,5
CLA MAE1
ADD KS2 INCREMENT ADDRESS
STO MAE1
CDS 1,11
TRA MAD1
MAH1 STO 777
CLA =O000000360 DELAY 20 MSEC.
SUB K1
TNZ *-1
HOP 777
# PAGE 148, SEQUENCE 75430-75990
# The following line is not in the original source code. I'm
# adding it as a workaround for what may be a bug in the original
# assembler that I haven't yet figured out how to mimic in the
# modern assembler.
DOG 1,11,136 # workaround
MDATA OCT 000016524
OCT 000012524
OCT 000002524
OCT 000006524
OCT 000007524
OCT 000006524
OCT 000004524
OCT 000005524
OCT 000005724
OCT 000005524
OCT 000005124
OCT 000005324
OCT 000005364
OCT 000005324
OCT 000005224
OCT 000005264
OCT 000005274
OCT 000005264
OCT 000005244
OCT 000005254
OCT 000005256
OCT 000005254
OCT 000005250
OCT 000005252
K100A OCT 000006540 2.612 VDC
K100B OCT 000010520 3.381 VDC
K100C OCT 000006100 2.392 VDC
K100D OCT 000011160 3.601 VDC
K100E OCT 000106320 27.50 VDC
K100F OCT 000110740 28.49 VDC
K100G OCT 000051760 16.39 VDC
K100H OCT 000047740 15.60 VDC
K100J OCT 000025200 8.30 VDC
K100K OCT 000023560 7.70 VDC
JXG1 CLA =O000040000 BIT 12
CIO 623
* CHECK TELEMETRY CHANNELS A/D
JXF2 STO 776
CLA =O000012070
CIO 022 LOAD DIN REG
CLA =O000100000 BIT 11
CIO 613
TRA MAH1 DELAY
CIO 303 SEL + 20 VDC TEL CHANNEL
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100A
TMI JXJ5
STO 776
CLA K100B
SUB TEMP
TMI JXJ5
JXJ2 STO 776
CIO 313 SEL + 12 VDC TEL CHL
CIO 025 READ A/D CONVERTER
# PAGE 149, SEQUENCE 76000-76560
STO TEMP
SUB K100A
TMI JXJ5
STO 776
CLA K100B
SUB TEMP
TMI JXJ5
JXA3 STO 776
CIO 323 SEL + 6 VDC TEL CHL
CIO 025 READ A/D CONVERTER
SUB K100C
TMI *+2
TRA JXJ5
JXB3 STO 776
CIO 333 SEL + 6 VDC SIG TEL CHL
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100A
TMI JXJ5
STO 776
CLA K100B
SUB TEMP
TMI JXJ5
JXD3 STO 776
CIO 343
CIO 025 READ A/D CONVERTER
SUB K100D
TMI JXJ5
JXE3 STO 776
CIO 353 SEL -20 VDC TEL CHL
CIO 025 READ A/D CONVERTER
SUB K100C
TMI *+2
TRA JXJ5
JXG3 STO 776
CLA =O000100000 BIT 11
CIO 623
CLA =O000040000 BIT 12
CIO 623
CLA =O000005322
CIO 022 LOAD DIN REG
CLA =O000100000 BIT 11
CIO 613
TRA MAH1 DELAY
CIO 303 SEL + 20 VDC TEL CHANNEL
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100A
TMI JXJ5
STO 776
CLA K100B
SUB TEMP
TMI JXJ5
JXJ3 STO 776
CIO 313 SEL + 12 VDC TEL CHL
CIO 025 READ A/D CONVERTER
STO TEMP
# PAGE 150, SEQUENCE 76570-77130
SUB K100A
TMI JXJ5
STO 776
CLA K100B
SUB TEMP
TMI JXJ5
JZA1 STO 776
CIO 323 SEL + 6 VDC TEL CHL
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100A
TMI JXJ5
STO 776
CLA K100B
SUB TEMP
TMI JXJ5
JZC1 STO 776
CIO 333 SEL + 6 VDC SIG TEL CHL
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100A
TMI JXJ5
STO 776
CLA K100B
SUB TEMP
TMI JXJ5
JZE1 STO 776
CIO 343 SEL - 6 VDC TEL CHL
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100A
TMI JXJ5
STO 776
CLA K100B
SUB TEMP
TMI JXJ5
JZG1 STO 776
CIO 353 SEL -20 VDC TEL CHL
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100A
TMI JXJ5
STO 776
CLA K100B
SUB TEMP
TMI JXJ5
TRA JZJ1
ORG 1,5,1,20,1,11,
JZJ1 CLA =O0001 BIT 11
STO 776
CIO 623
CLA =O000040000 BIT 12
CIO 623
CLA =O000003416
CIO 022 LOAD DIN REG
CLA =O000100000 BIT 11
CIO 613
# PAGE 151, SEQUENCE 77140-77700
TRA MAH1 DELAY
CIO 303 SEL + 20 VDC TEL CHANNEL
CIO 025 READ A/D CONVERTER
SUB K100C
TMI *+2
TRA JXJ5
JZA2 STO 776
CIO 313 SEL + 12 VDC TEL CHL
CIO 025 READ A/D CONVERTER
SUB K100D
TMI JXJ5
JZB2 STO 776
CIO 323 SEL + 6 VDC TEL CHL
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100A
TMI JXJ5
STO 776
CLA K100B
SUB TEMP
TMI JXJ5
JZD2 STO 776
CIO 333 SEL + 6 VDC SIG TEL CHL
CIO 025 READ A/D CONVERTER
SUB K100C
TMI *+2
TRA JXJ5
JZE2 STO 776
CIO 343 SEL - 6 VDC TEL CHL
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100A
TMI JXJ5
STO 776
CLA K100B
SUB TEMP
TMI JXJ5
JZG2 STO 776
CIO 353 SEL -20 VDC TEL CHL
CIO 025 READ A/D CONVERTER
SUB K100D
TMI JXJ5
JZH2 STO 776
CLA =O000100000 BIT 11
CIO 623
CLA =O000040000 BIT 12
CIO 623
CLA =O000014744
CIO 022 LOAD DIN REG
CLA =O000100000 BIT 11
CIO 613
TRA MAH1 DELAY
CIO 303 SEL + 20 VDC TEL CHANNEL
CIO 025 READ A/D CONVERTER
SUB K100D
TMI JXJ5
JZK2 STO 776
# PAGE 152, SEQUENCE 77710-78270
CIO 313 SEL + 12 VDC TEL CHL
CIO 025 READ A/D CONVERTER
SUB K100C
TMI *+2
TRA JXJ5
JZA3 STO 776
CIO 323 SEL + 6 VDC STEL CHL
CIO 025 READ A/D CONVERTER
SUB K100D
TMI JXJ5
JZB3 STO 776
CIO 333 SEL + 6 VDC SIG TEL CHL
CIO 025 READ A/D CONVERTER
SUB K100D
TMI JXJ5
JZC3 STO 776
CIO 343 SEL - 6 VDC TEL CHL
CIO 025 READ A/D CONVERTER
SUB K100C
TMI *+2
TRA JXJ5
JZD3 STO 776
CIO 353 SEL -20 VDC TEL CHL
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100A
TMI JXJ5
STO 776
CLA K100B
SUB TEMP
TMI JXJ5
* CHECK VOLTAGE SWITCHING ON + 28 SIG
JZF3 STO 776
CLA =O000100000 BIT 11
CIO 623
CLA =O000040000 BIT 12
CIO 623
CLA =O000012524
CIO 022 LOAD DIN REG
CLA =O000100000 BIT 11
CIO 613
CLA =O000000400 BIT 18
CIO 623
CLA =O000001000 BIT 17
CIO 623
TRA MAJ1 DELAY
TRA MAJ1 DELY
CIO 453 SEL + 28 SIG
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100E
TMI JXJ5 LESS THAN 27.5
STO 776
CLA K100F
SUB TEMP
TMI JXJ5
# PAGE 153, SEQUENCE 78280-78840
JZJ3 STO 776
CLA K1
CIO 613
JZK3 STO 776
TRA MAJ1 DELAY
TRA MAJ1 DELY
CIO 453 SEL + 28 SIG
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100H
TMI JXJ5
STO 776
CLA K100G
SUB TEMP
TMI JXJ5
JZB4 STO 776
CLA =O000000400 BIT 18
CIO 623
TRA MAJ1 DELAY
TRA MAJ1 DELY
CIO 453 SEL + 28 SIG
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100E
TMI JXJ5
STO 776
CLA K100F
SUB TEMP
TMI JXJ5
JZD4 STO 776
CLA =O000000004 BIT 24
CIO 613
TRA MAJ1 DELAY
TRA MAJ1 DELY
CIO 453 SEL + 28 SIG
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100K
TMI JXJ5
STO 776
CLA K100J
SUB TEMP
TMI JXJ5
JZG4 STO 776
CLA =O000001000 BIT 17
CIO 623
TRA MAJ1 DELAY
TRA MAJ1 DELY
CIO 453 SEL + 28 SIG
CIO 025 READ A/D CONVERTER
STO TEMP
SUB K100E
TMI JXJ5
STO 776
CLA K100F
SUB TEMP
TMI JXJ5
# PAGE 154, SEQUENCE 78850-78910
CLA =O000100000 BIT 11
CIO 623
CLA =O000040000 BIT 12
CIO 623
HOP H2P1
JXJ5 STO 777
TRA JAJ5A
# PAGE 155, SEQUENCE 78930-79490
ORG 1,7,1,40,1,13,2
* ROUTINE 11
* CHANNEL SWITCHING TEST LVDA-ME
* SEE PROCEDURE FOR PROPER VISUAL PATTERN
NAB1 CLA LCR11
TMI NAC1
CLA LC8
TMI NAB1C
NAB1D STO LC8
NAB1A TRA JAB1 TO RTN 9 AND 10
NAB1C TRA NAF1
CLA =O000002200 RESET TBL AND PWR TEST
CIO 623
CLA ZERO
CIO 022
CIO 042
CIO 036
TRA NAB1D
NAC1 CLA TIME
ADD =O000000002
STO TIME
SUB =O000000024 TEN
TNZ NAB1A
STO TIME SET EQUAL TO ZERO
STO LC8
TRA NAF1
TRA NAG1A
NAF1 STO 777
* CAL POINT NR 26
CLA =O000004000 RESET S.I.
CIO 623
NAG1 CLA =O000000012 BITS 23,25
CIO 603 SET TMR
CLA =O000010000 BIT 14
CIO 623 RESET DD ERRORS
CIO 066
HOP 777
NAG1A CLA =O000100000 SET INT 15 INHIBIT
CIO 000
NAH1 STO 776
CLA =O000000040 BIT 21
CIO 633 FULL SEQUENCE
CLA =O000001622 DELAY 75 MSEC.
SUB K1
TNZ *-1
CIO 154
AND =O000010000
TNZ NAJ5
STO 776
CLA =O000000266 DELAY 15 MSEC.
NAH1A SUB K1
TNZ NAH1A
* SHOULD GET INT 15 BEFORE END OF COUNT
CIO 154
AND =O000010000
TNZ NAK1
TRA NAJ5
# PAGE 156, SEQUENCE 79500-80060
NAK1 CIO 100
CIO 110
TRA NAB1A TO JAB1
NAJ5 STO 777
TRA JAJ5A
NAB2 CLA LCR11
TMI NAC2
TNZ PAB1A
NAB2A HOP H2P1
PAB1A TRA PAB1
NAC2 CLA TIME
TNZ NAB2A
NAD2 STO 776
CLA =O000100000 SET INT 15 INHIBIT
CIO 000
CLA =O000000100 BIT 20
CIO 633 HALF SEQUENCE
CLA =O000000074 DELAY 5 MSEC.
SUB K1
TNZ *-1
CIO 154
AND =O000010000
TNZ NAJ5
STO 776
CLA =O000000074 DELAY 5 MSEC.
NAD2A SUB K1
TNZ NAD2A
* SHOULD GET INT 15 BEFORE END OF COUNT
CIO 154
AND =O000010000
TNZ NAF2
TRA NAJ5
NAF2 CIO 100
CIO 110
CLA HJAJ5
STO 404
CLA =O400000000
CIO 066 ENABLE COMPARE
STO LC8 CHANNEL SWITCHING IN PROGRESS
CLA CSCTR
TNZ NAB3
* CAL POINT NR 27
CDS 1,7
CLA NAB3
AND KX1 REMOVE ADDRESS
STO TEMP
CLA KNAB3
AND KX6 KEEP ADDRESS
XOR TEMP
STO NAB3
CLA NAC3
AND KX1 REMOVE ADDRESS
STO TEMP
CLA KNAC3
AND KX6 KEEP ADDRESS
XOR TEMP
STO NAC3
# PAGE 157, SEQUENCE 80070-80630
CDS 1,13
NAB3 CLA KD1
STO VAR5 ERROR INFO
CIO 022 LOAD DIN REG
CIO 071 READ DIN REG
CDS 1,12
NAC3 CLA KEM1
STO VAR4 ERROR INFO
CIO 042 LOAD EM REG
CIO 111 READ EM REG
CDS 1,7
CLA NAB3
ADD KS1 INCREMENT ADDRESS
STO NAB3
CLA NAC3
ADD KS1 INCREMENT ADDRESS
STO NAC3
CDS 1,13
NAE3 CLA CSCTR
ADD K1 INCREMENT CTR
STO CSCTR
SUB =O000000406 =131 DEC.
TMI NAF3
NAB4 CLA =O000030000 BITS 13,14
CIO 613
CLA CSCTR
SUB =O000000530 =172 DEC.
TNZ NAB5
NAD4 STO CSCTR =0
TRA NAB5
KNAB3 CLA KD1
DOG 1,12,0
KNAC3 CLA KEM1
DOG 1,13,
NAF3 CLA CSCTR
SUB =O000000262 =89 DEC.
TMI NAG3 LESS THAN 89
NAF4 CLA =O000024000 BITS 13,15
CIO 613
TRA NAB5
NAG3 CLA CSCTR
SUB =O000000136 =47 DEC.
TMI NAH3 LESS THAN 47
NAG4 CLA =O000022000 BITS 13,16
CIO 613 SET CH2
TRA NAB5
NAH3 CLA CSCTR
SUB =O000000012 =5
TMI NAJ3 LESS THAN 5
NAH4 CLA =O000021000 BITS 13,17
CIO 613
TRA NAB5
NAJ3 CLA CSCTR
SUB =O000000004 =2
TMI NAH4
TNZ *+2
TRA NAG4
# PAGE 158, SEQUENCE 80640-81200
SUB K1 =1
TNZ NAB4
TRA NAF4
NAB5 STO 776
CLA =O000000360
NAB5A SUB K1
TNZ NAB5A
CIO 154
AND =O000010000
TNZ NAJ5
NAD5 STO 776
CLA =O000000074
SUB K1
TNZ *-1
CIO 154
AND =O000010000
TNZ NAD5A
HOP HJAJ5
NAD5A CIO 100
TRA NBA1
* TEST DISAGREEMENT DETECTORS AND CHANNEL
* ERROR INDICATORS
ORG 1,7,0,40,1,13,
NBA1 CLA DDCTR
ADD K1 INCREMENT CTR
STO DDCTR
SUB =O000000004
TMI NBC2 DDCTR = 1
SUB K1
TMI NBD2 DDCTR = 2
SUB K1
TMI NBE2 DDCTR = 3
SUB K1
TMI NBF2 DDCTR = 4
SUB K1
TMI NBG2 DDCTR = 5
NBH1 STO DDCTR DDCTR=6
NBH2 STO 776
CLA =O000002000
CIO 623
CLA =O000000040
CIO 603 INACTIVE CHL = 1
CLA =O222000000
CIO 036 LOAD DDAS
CIO 105 READ DDAS
CLA =O000010000
CIO 623
CLA =O000000014
CIO 603 SET CHL 3
CLA =O000000200 RESET PWR TEST
CIO 623
PIO 402
TRA NBG4
NBC2 STO 776
CLA =O000000100 INACTIVE CHL = 0
CIO 603
CLA =O333000000
# PAGE 159, SEQUENCE 81210-81770
CIO 036 LOAD DDAS
CIO 105 READ DDAS
CLA =O000010000
CIO 623
CLA =O000000024
CIO 603 SET CHL 1
CLA =O000000050 SET PWR TEST 1 AND TEL +8 IND
CIO 613
PIO 402
TRA NBC4
NBD2 STO 776
CLA =O000000100 INACTIVE CHL = 0
CIO 603
CLA =O266400000
CIO 036 DDAS
CIO 105
CLA =O000010000
CIO 623
CLA =O000000022
CIO 603 SET CHL 2
CLA =O000000100 SET PWR TEST 2
CIO 613
PIO 402
TRA NBC4
NBE2 STO 776
CLA =O000002000
CIO 623
CLA =O000000100
CIO 603 INACTIVE CHL = 0
CLA =O155400000
CIO 036
CIO 105
CLA =O000010000
CIO 623
CLA =O000000014 SET CHL 3
CIO 603
CLA =O000000200 SET PWR TEST 3
CIO 613
PIO 402
TRA NBC4
NBF2 STO 776
CLA =O000000040 INACTIVE CHL = 1
CIO 603
CLA =O044400000
CIO 036
CIO 105
CLA =O000010000
CIO 623
CLA =O000000024 SET CHL 1
CIO 603
CLA =O000000420 SET PWR TEST 4 AND TEL -8 IND
CIO 613
PIO 402
TRA NBC4
NBG2 STO 776
CLA =O000000040 INACTIVE CHL = 1
CIO 603
# PAGE 160, SEQUENCE 81780-82340
CLA =O111000000
CIO 036
CIO 105
CLA =O000010000
CIO 623
CLA =O000000022 SET CHL 2
CIO 603
CLA =O000000040 SET PWR TEST 1
CIO 613
PIO 402
NBC4 STO 776
CLA =O000000360 DELAY 20 MSEC.
SUB K1
TNZ *-1
CIO 154
AND =O000010000
TNZ NAJ5
NBE4 CLA =O000000074 DELAY 5 MSEC.
SUB K1
TNZ *-1
CIO 154
AND =O000010000
TNZ NBG4
HOP HJAJ5
NBG4 CIO 100
CIO 110
HOP H2P1
DOG 1,12,0
KEM1 OCT 774014000
KEM2 OCT 777760000
KEM3 OCT 777760000
KEM4 OCT 777774000
KEM5 OCT 774014000
KEM6 OCT 774014000
KEM7 OCT 774014000
KEM8 OCT 774014000
KEM9 OCT 774014000
KEM10 OCT 774010000
KEM11 OCT 774004000
KEM12 OCT 774014000
KEM13 OCT 774014000
KEM14 OCT 774014000
KEM15 OCT 774014000
KEM16 OCT 774014000
KEM17 OCT 774014000
KEM18 OCT 774014000
KEM19 OCT 774034000
KEM20 OCT 774054000
KEM21 OCT 774114000
KEM22 OCT 774214000
KEM23 OCT 774414000
KEM24 OCT 775014000
KEM25 OCT 776014000
KEM26 OCT 774014000
KEM27 OCT 774014000
KEM28 OCT 774014000
KEM29 OCT 774014000
# PAGE 161, SEQUENCE 82350-82910
KEM30 OCT 774014000
KEM31 OCT 774014000
KEM32 OCT 774014000
KEM33 OCT 770014000
KEM34 OCT 764014000
KEM35 OCT 754014000
KEM36 OCT 734014000
KEM37 OCT 674014000
KEM38 OCT 574014000
KEM39 OCT 374014000
KEM40 OCT 774014000
KEM41 OCT 774014000
KEM42 OCT 774014000
KEM43 OCT 774014000
KEM44 OCT 774014000
KEM45 OCT 774014000
KEM46 OCT 774014000
KEM47 OCT 777760000
KEM48 OCT 777760000
KEM49 OCT 777760000
KEM50 OCT 777760000
KEM51 OCT 777760000
KEM52 OCT 777764000
KEM53 OCT 777770000
KEM54 OCT 777760000
KEM55 OCT 777760000
KEM56 OCT 777760000
KEM57 OCT 777760000
KEM58 OCT 777760000
KEM59 OCT 777760000
KEM60 OCT 777760000
KEM61 OCT 777740000
KEM62 OCT 777720000
KEM63 OCT 777660000
KEM64 OCT 777560000
KEM65 OCT 777360000
KEM66 OCT 776760000
KEM67 OCT 775760000
KEM68 OCT 777760000
KEM69 OCT 777760000
KEM70 OCT 777760000
KEM71 OCT 777760000
KEM72 OCT 777760000
KEM73 OCT 777760000
KEM74 OCT 777760000
KEM75 OCT 773760000
KEM76 OCT 767760000
KEM77 OCT 757760000
KEM78 OCT 737760000
KEM79 OCT 677760000
KEM80 OCT 577760000
KEM81 OCT 377760000
KEM82 OCT 777760000
KEM83 OCT 777760000
KEM84 OCT 777760000
KEM85 OCT 777760000
KEM86 OCT 777760000
# PAGE 162, SEQUENCE 82920-83480
KEM87 OCT 777760000
KEM88 OCT 777760000
KEM89 OCT 777760000
KEM90 OCT 777760000
KEM91 OCT 777760000
KEM92 OCT 777760000
KEM93 OCT 777760000
KEM94 OCT 777764000
KEM95 OCT 777770000
KEM96 OCT 777760000
KEM97 OCT 777760000
KEM98 OCT 777760000
KEM99 OCT 777760000
KEM100 OCT 777760000
KEM101 OCT 777760000
KEM102 OCT 777760000
KEM103 OCT 777740000
KEM104 OCT 777720000
KEM105 OCT 777660000
KEM106 OCT 777560000
KEM107 OCT 777360000
KEM108 OCT 776760000
KEM109 OCT 775760000
KEM110 OCT 777760000
KEM111 OCT 777760000
KEM112 OCT 777760000
KEM113 OCT 777760000
KEM114 OCT 777760000
KEM115 OCT 777760000
KEM116 OCT 777760000
KEM117 OCT 773760000
KEM118 OCT 767760000
KEM119 OCT 757760000
KEM120 OCT 737760000
KEM121 OCT 677760000
KEM122 OCT 577760000
KEM123 OCT 377760000
KEM124 OCT 777760000
KEM125 OCT 777760000
KEM126 OCT 777760000
KEM127 OCT 777760000
KEM128 OCT 777760000
KEM129 OCT 777760000
KEM130 OCT 777760000
KEM131 OCT 777774000
KEM132 OCT 777774000
KEM133 OCT 777774000
KEM134 OCT 777774000
KEM135 OCT 777774000
KEM136 OCT 777770000
KEM137 OCT 777764000
KEM138 OCT 777774000
KEM139 OCT 777774000
KEM140 OCT 777774000
KEM141 OCT 777774000
KEM142 OCT 777774000
KEM143 OCT 777774000
# PAGE 163, SEQUENCE 83490-84050
KEM144 OCT 777774000
KEM145 OCT 777754000
KEM146 OCT 777734000
KEM147 OCT 777674000
KEM148 OCT 777574000
KEM149 OCT 777374000
KEM150 OCT 776774000
KEM151 OCT 775774000
KEM152 OCT 777774000
KEM153 OCT 777774000
KEM154 OCT 777774000
KEM155 OCT 777774000
KEM156 OCT 777774000
KEM157 OCT 777774000
KEM158 OCT 777774000
KEM159 OCT 773774000
KEM160 OCT 767774000
KEM161 OCT 757774000
KEM162 OCT 737774000
KEM163 OCT 677774000
KEM164 OCT 577774000
KEM165 OCT 377774000
KEM166 OCT 777774000
KEM167 OCT 777774000
KEM168 OCT 777774000
KEM169 OCT 777774000
KEM170 OCT 777774000
KEM171 OCT 777774000
KEM172 OCT 777774000
# The following line is what appeared in the original listing, uncommented.
# I've commented out and replaced it, because it doesn't have the effect
# I think it's supposed to. I think this may be a bug in the original
# assembler.
# DOG 1,13,
DOG 1,13,5 # workaround
KD1 OCT 740177776
KD2 OCT 000177774
KD3 OCT 037600774
KD4 OCT 777777776
KD5 OCT 700177776
KD6 OCT 640177776
KD7 OCT 540177776
KD8 OCT 340177776
KD9 OCT 740177774
KD10 OCT 740177776
KD11 OCT 740177776
KD12 OCT 740177772
KD13 OCT 740177766
KD14 OCT 740177756
KD15 OCT 740177736
KD16 OCT 740177676
KD17 OCT 740177576
KD18 OCT 740177376
KD19 OCT 740177776
KD20 OCT 740177776
KD21 OCT 740177776
KD22 OCT 740177776
KD23 OCT 740177776
KD24 OCT 740177776
KD25 OCT 740177776
KD26 OCT 740176776
KD27 OCT 740175776
# PAGE 164, SEQUENCE 84060-84620
KD28 OCT 740173776
KD29 OCT 740167776
KD30 OCT 740157776
KD31 OCT 740137776
KD32 OCT 740077776
KD33 OCT 740177776
KD34 OCT 740177776
KD35 OCT 740177776
KD36 OCT 740177776
KD37 OCT 740177776
KD38 OCT 740177776
KD39 OCT 740177776
KD40 OCT 740377776
KD41 OCT 740577776
KD42 OCT 741177776
KD43 OCT 742177776
KD44 OCT 744177776
KD45 OCT 750177776
KD46 OCT 760177776
KD47 OCT 040177774
KD48 OCT 100177774
KD49 OCT 200177774
KD50 OCT 400177774
KD51 OCT 000177776
KD52 OCT 000177774
KD53 OCT 000177774
KD54 OCT 000177770
KD55 OCT 000177764
KD56 OCT 000177754
KD57 OCT 000177734
KD58 OCT 000177674
KD59 OCT 000177574
KD60 OCT 000177374
KD61 OCT 000177774
KD62 OCT 000177774
KD63 OCT 000177774
KD64 OCT 000177774
KD65 OCT 000177774
KD66 OCT 000177774
KD67 OCT 000177774
KD68 OCT 000176774
KD69 OCT 000175774
KD70 OCT 000173774
KD71 OCT 000167774
KD72 OCT 000157774
KD73 OCT 000137774
KD74 OCT 000077774
KD75 OCT 000177774
KD76 OCT 000177774
KD77 OCT 000177774
KD78 OCT 000177774
KD79 OCT 000177774
KD80 OCT 000177774
KD81 OCT 000177774
KD82 OCT 000377774
KD83 OCT 000577774
KD84 OCT 001177774
# PAGE 165, SEQUENCE 84630-85190
KD85 OCT 002177774
KD86 OCT 004177774
KD87 OCT 010177774
KD88 OCT 020177774
KD89 OCT 077600774
KD90 OCT 137600774
KD91 OCT 237600774
KD92 OCT 437600774
KD93 OCT 037600776
KD94 OCT 037600774
KD95 OCT 037600774
KD96 OCT 037600770
KD97 OCT 037600764
KD98 OCT 037600754
KD99 OCT 037600734
KD100 OCT 037600674
KD101 OCT 037600574
KD102 OCT 037600374
KD103 OCT 037600774
KD104 OCT 037600774
KD105 OCT 037600774
KD106 OCT 037600774
KD107 OCT 037600774
KD108 OCT 037600774
KD109 OCT 037600774
KD110 OCT 037601774
KD111 OCT 037602774
KD112 OCT 037604774
KD113 OCT 037610774
KD114 OCT 037620774
KD115 OCT 037640774
KD116 OCT 037700774
KD117 OCT 037600774
KD118 OCT 037600774
KD119 OCT 037600774
KD120 OCT 037600774
KD121 OCT 037600774
KD122 OCT 037600774
KD123 OCT 037600774
KD124 OCT 037400774
KD125 OCT 037200774
KD126 OCT 036600774
KD127 OCT 035600774
KD128 OCT 033600774
KD129 OCT 027600774
KD130 OCT 017600774
KD131 OCT 737777776
KD132 OCT 677777776
KD133 OCT 577777776
KD134 OCT 377777776
KD135 OCT 777777774
KD136 OCT 777777776
KD137 OCT 777777776
KD138 OCT 777777772
KD139 OCT 777777766
KD140 OCT 777777756
KD141 OCT 777777736
# PAGE 166, SEQUENCE 85200-85760
KD142 OCT 777777676
KD143 OCT 777777576
KD144 OCT 777777376
KD145 OCT 777777776
KD146 OCT 777777776
KD147 OCT 777777776
KD148 OCT 777777776
KD149 OCT 777777776
KD150 OCT 777777776
KD151 OCT 777777776
KD152 OCT 777776776
KD153 OCT 777775776
KD154 OCT 777773776
KD155 OCT 777767776
KD156 OCT 777757776
KD157 OCT 777737776
KD158 OCT 777677776
KD159 OCT 777777776
KD160 OCT 777777776
KD161 OCT 777777776
KD162 OCT 777777776
KD163 OCT 777777776
KD164 OCT 777777776
KD165 OCT 777777776
KD166 OCT 777577776
KD167 OCT 777377776
KD168 OCT 776777776
KD169 OCT 775777776
KD170 OCT 773777776
KD171 OCT 767777776
KD172 OCT 757777776
* ROUTINE 12
* CHECK COD SIMULATION UNDER MANUAL CONTROL
ORG 1,6,1,30,1,10,101
PAB1 CLA LCR12
TMI PAC1
HOP H2P1
* INITIALIZE
PAC1 CLA ZERO
STO CTR
CIO 204
CIO 210
STO QUAD1
STO QUAD2
STO QUAD3
STO QUAD4
STO MAG
STO STOP
CLA K77
STO PATH
CLA Y1
STO YN INITIALIZE Y
Y1 OCT 001000000 BIT 8
CDS 1,6
CLA KPAF1 INITIALIZE X
AND KX6
STO TEMP
# PAGE 167, SEQUENCE 85770-86330
CLA PAF1
AND KX1
XOR TEMP
STO PAF1
CLA PAH1
AND KX1
XOR TEMP
STO PAH1
CLA PAD2
AND KX1
XOR TEMP
STO PAD2
CLA PAF2
AND KX1
XOR TEMP
STO PAF2
CDS 1,10
PAD1 CLA YN SELECT PATH YN
CIO 007
PAE1 CLA =O000000652 DELAY 35 MSEC.
SUB K1
TNZ *-1
* LOAD RATIOTRAN A=XN
PAF1 CLA X1
CIO 017
CLA =O000000652 DELAY 35 MSEC.
SUB K1
TNZ *-1
* LOAD RATIOTRAN B=XN
PAH1 CLA X1
CIO 017
CLA PATH
TMI PBF2
CIO 114 SET SINGLE STEP
* MANUAL OPERATION
* READ RATIOTRAN
* SET SWITCH B3 ON IF TEST IS TO BE REPEATED
* DEPRESS ADVANCE
TRA PCH1
PAC2 CIO 220 IS REPEAT SWITCH ON
AND =O040000000
TNZ PAE1 YES
* LOAD RATIOTRAN=XN
PAD2 CLA X1
CIO 017
CIO 114 SINGLE STEP
* MANUAL OPERATION
* READ RATIOTRAN
* SET SWITCH B3 ON IF TEST IS TO BE REPEATED
* DEPRESS ADVANCE
TRA PCH1
PAF2 CLA X1 LOAD RATIOTRAN B
CIO 017
PAG2 CIO 220
AND =O040000000 IS REPEAT SWITCH ON
TNZ PAE1
PAH2 CLA YN INCREMENT PATH SELECT
# PAGE 168, SEQUENCE 86340-86890
SHR 1
STO YN
PAJ2 CLA PATH
TMI PBA1
CLA Y1
STO YN
TRA PBD1
PBA1 CLA YN IS PATH TEST COMPLETE
TNZ PAD1
PBB1 STO PATH
CLA K77
STO QUAD1
CLA Y1 SELECT PATH Y1
CIO 007
CLA =O000000652 DELAY 35 MSEC.
SUB K1
TNZ *-1
PBD1 CLA QUAD1
TMI PBF1
TRA PBB3
* QUADRANT 1 TESTS
PBF1 CLA X1 LOAD RATIOTRAN=XN
CIO 177 TRY TO SET MINUS WITH BIT S=0,1=0
CLA =O000000652
SUB K1
TNZ *-1
CLA X1
CIO 177 TRY TO SET MINUS WITH BIT S=0,1=0
CLA ZERO
STO QUAD1
CLA K77
STO QUAD2
TRA PAE1
KPAF1 CLA X1
CA OCT 577777776
CB OCT 777777776
CC OCT 377777776
PBF2 CLA CA SELECTS QUAD 2
CIO 077
CIO 114 SINGLE STEP
* MANUAL OPERATION
* CHECK FOR 10 VRMS ON CORRECT PATH
* SET SWITCH B3 ON IF TEST IS TO BE REPEATED
* DEPRESS ADVANCE
TRA PCH1
CIO 220
AND =O040000000
TNZ PAJ2
TRA PAH2
PBB3 CLA QUAD2
TMI PCB1
CLA QUAD3
TMI PCE1
CLA QUAD4
TMI PCB2
CLA MAG
# PAGE 169, SEQUENCE 86900-87460
TMI PBF3
HOP H2P1
PBF3 CLA =O000000030 RESET COD SINA,SINB
CIO 623
CDS 1,6
CLA PAF1
ADD KS1
STO PAF1
CLA PAH1
ADD KS1
STO PAH1
CLA PAD2
ADD KS1
STO PAD2
CLA PAF2
ADD KS1
STO PAF2
CDS 1,10
CLA STOP
ADD KS1
STO STOP
SUB =O072000000
TNZ PAE1
STO MAG
TRA PAE1
PCB1 CLA CC QUADRANT 2 TESTS
CIO 117 LOADS RATIOTRAN=B
CIO 114 READ B
TRA PCH1
CLA CC
CIO 117 LOADS RATIOTRAN=A
CIO 114 READ A
TRA PCH1
CLA =O000000300 RESETS COSA AND COSB
CIO 623
CLA CA SETS COSB MINUS
CIO 057 LOAD RATIOTRAN=B
CIO 114
TRA PCH1
CLA CA SES COSA MINUS
CIO 037 LOAD RATIOTRAN=A
CIO 114
TRA PCH1
CLA K77
STO QUAD3
CLA ZERO
STO QUAD2
TRA PCF1
PCE1 CLA CB QUADRANT 3 TESTS
CIO 117 LOADS RATIOTRAN=B
CIO 114 READ B
TRA PCH1
CLA CB
CIO 117 LOADS RATIOTRAN=A
CIO 114 READ A
TRA PCH1
CLA =O000000170 RESETS SINA COSA,SINB COSB
# PAGE 170, SEQUENCE 87470-88030
CIO 623
CLA CB SET SINB AND COSB MINUS
CIO 057 LOAD RATIOTRAN=B
CIO 114
TRA PCH1
CLA CB SET SINA AND COSA MINUS
CIO 037 LOAD RATIOTRAN=A
CIO 114
TRA PCH1
CLA K77
STO QUAD4
CLA ZERO
STO QUAD3
TRA PCF1
PCB2 CLA CA QUADRANT 4 TESTS
CIO 117 LOAD RATIOTRAN=B
CIO 114 READ B
TRA PCH1
CLA CA
CIO 117 LOADS RATIOTRAN=A
CIO 114 READ A
TRA PCH1
CLA =O000000030 RESETS SINA AND SINB
CIO 623
CLA CC SETS SINB MINUS
CIO 057 LOADS RATIOTRAN=B
CIO 114
TRA PCH1
CLA CC SETS SINA MINUS
CIO 037 LOADS RATIOTRAN=A
CIO 114
TRA PCH1
CLA K77
STO MAG
CLA ZERO
STO QUAD4
PCF1 CLA =O000000170
CIO 623
TRA PBB3
PCH1 STO 776
CLA CTR
ADD K1
STO CTR
CIO 204
AND =O000000176
TNZ *+3
CLA K1
CIO 210
HOP 776
X1 OCT 177777774
OCT 000160016
OCT 000140014
OCT 000120012
OCT 000100010
OCT 000060006
OCT 000040004
OCT 000020002
# PAGE 171, SEQUENCE 88040-88260
OCT 001600160
OCT 001400140
OCT 001200120
OCT 001000100
OCT 000600060
OCT 000400040
OCT 000200020
OCT 016001600
OCT 014001400
OCT 012001200
OCT 010001000
OCT 006000600
OCT 004000400
OCT 002000200
OCT 160016000
OCT 140014000
OCT 120012000
OCT 100010000
OCT 060006000
OCT 040004000
OCT 020002000
OCT 000000000
END
