From 64d1e8b748bca22ce205eab7634cc5418c827f18 Mon Sep 17 00:00:00 2001
From: Marina Yatsina <marina.yatsina@intel.com>
Date: Thu, 21 Jul 2016 12:37:07 +0000
Subject: [PATCH 3/5] ExecutionDepsFix - Fix bug in clearance calculation

The clearance calculation did not take into account registers defined as outputs or clobbers in inline assembly machine instructions because these register defs are implicit.

Differential Revision: http://reviews.llvm.org/D22580



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@276266 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/CodeGen/ExecutionDepsFix.cpp    |  2 --
 test/CodeGen/X86/break-false-dep.ll | 10 ++++++++++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/lib/CodeGen/ExecutionDepsFix.cpp b/lib/CodeGen/ExecutionDepsFix.cpp
index 566b8d507b2..1fe5f459b69 100644
--- a/lib/CodeGen/ExecutionDepsFix.cpp
+++ b/lib/CodeGen/ExecutionDepsFix.cpp
@@ -520,8 +520,6 @@ void ExeDepsFix::processDefs(MachineInstr *MI, bool Kill) {
     MachineOperand &MO = MI->getOperand(i);
     if (!MO.isReg())
       continue;
-    if (MO.isImplicit())
-      break;
     if (MO.isUse())
       continue;
     for (int rx : regIndices(MO.getReg())) {
diff --git a/test/CodeGen/X86/break-false-dep.ll b/test/CodeGen/X86/break-false-dep.ll
index 74a0728f918..a7cda499dab 100644
--- a/test/CodeGen/X86/break-false-dep.ll
+++ b/test/CodeGen/X86/break-false-dep.ll
@@ -199,3 +199,13 @@ for.end16:                                        ; preds = %for.inc14
 ;AVX-NEXT: vmulsd {{.*}}, [[XMM0]], [[XMM0]]
 ;AVX-NEXT: vmovsd [[XMM0]],
 }
+
+define double @inlineasmdep(i64 %arg) {
+top:
+  tail call void asm sideeffect "", "~{xmm0},~{dirflag},~{fpsr},~{flags}"()
+  %tmp1 = sitofp i64 %arg to double
+  ret double %tmp1
+;AVX-LABEL:@inlineasmdep
+;AVX: vxorps  [[XMM0:%xmm[0-9]+]], [[XMM0]], [[XMM0]]
+;AVX-NEXT: vcvtsi2sdq {{.*}}, [[XMM0]], {{%xmm[0-9]+}}
+}
-- 
2.11.0