AGC_BLOCK_II_INTERPRETIVE_CODES_ASSEMBLY_RULES_FOR_AGC.argus
# Copyright: Public domain.
# Filename: AGC_BLOCK_II_INTERPRETIVE_CODES_ASSEMBLY_RULES_FOR_AGC.mitigus
# Purpose: Part of the source code for YUL (revision 9).
# Assembler: TBD
# Contact: Jim Lawton <jim.lawton@gmail.com>
# Website: https://www.ibiblio.org/apollo/index.html
# Page scans: https://archive.org/details/yulsystemsourcec00hugh
# Pages: 018-023 (6)
# Mod history: 2016-10-06 JL Created.
# 2016-10-08 JL Transcribed.
# Annotations:
#
# B L A I R - S M I T H
# Y U L S Y S T E M
#
# Listings in
# MITIGUS Format
#
# Note: Page numbers are scan page numbers rather than listing.
L @AGC BLOCK II INTERPRETIVE CODES: ASSEMBLY RULES FOR AGC
# Page 18
# @AGC BLOCK II INTERPRETIVE CODES: ASSEMBLY RULES FOR AGC USER'S OWN PAGE NO. 1 PAGE 15
R0001 SUFFIX 01 CODES, INDEXABLE (EXCEPT SETPD) BY ADDING 10 TO SUFFIX. FOR A KEY TO DATA MODES, SEE PAGE 2.
R0002 ADDR PUSH MODE OP MODE RH OCT OCT* ALTERNATE ADDRESS CODES
R0003 TYPE UP IN MODE OUT OP CODE CODE SPELLING (167777 WILL BE LAST ACM ADDR)
0005 00 VLOAD A14 YES - V V 001 003 A14 ANY 14-BIT ADDRESS -- 0-52,
0007 01 TAD A14 YES DT T - 005 007 100-3777, IF LOCATION IN BANK
0009 02 SIGN E YES - D - 011 013 17 OR LESS THEN 20000-47776, IF
0011 *03 VXSC A14 YES DT/V V/D V 015 017 LOCATION IN BANK 21 OR MORE
0013 *04 CGOTO E+F NO - S U YES 021 023 THEN 52000-167777. STORED IN
0015 05 TLOAD A14 YES - T T 025 027 ARC-CCS FASHION, COMPLEMENTED
0017 06 DLOAD A14 YES - D D 031 033 IF INDEXED BY X2.
0019 07 V/SC A14 YES DT/V V/D V 035 037 *** SEE ALSO E & F BELOW. ***
0021 10 SLOAD A14 NO - S D 041 043 E ERASABLE -- 0-52, 100-3777.
0023 11 SSP E+C NO - S - 045 047 STORED IN ARC-CCS FASHION,
0025 12 PDDL A14 YES - D D 051 053 COMPLEMENTED IF INDEXED BY X2.
0027 13 MXV A14 NO V M - 055 057 *******************************
0029 14 PDVL A14 YES - V V 061 063 ALL INTERPRETIVE ADDRESSES
0031 15 CCALL E+F NO - S I YES 065 067 REFERRING TO ERASABLE ARE PUT
0033 16 VXM A14 NO V M - 071 073 INTO ECADR (11-BIT) FORM AND SO
0035 17 NORM E NO DT S - 075 077 SLC MAY REFER TP ANY E-BANK.
0036 20 DMPR A14 YES DT D D 101 103 F FIXED -- 20000-167777. STORED
0038 21 DDV A14 YES DT D - 105 107 AS IS. ***********************
0040 22 BDDV A14 YES DT D - 111 113 ALL INTERPRETIVE ADDRESSES
0042 23 (GEN SHIFT) REFERRING TO FIXED ARE PUT INTO
0044 24 VAD A14 YES V V - 121 123 FCADR FORM BEFORE ALTERATIONS
0046 25 VSU A14 YES V V - 125 127 SUCH AS TRUNCATING TO 14 BITS.
0048 26 BVSU A14 YES V V - 131 133
0049 27 DOT A14 YES V V D 135 137 V VAC AREA -- 0-52, ARC-CCS.
0050 30 VXV A14 YES V V - 141 143 C CONSTANT -- ANY TYPE OF SINGLE-
0052 31 VPROJ A14 YES V V - 145 147 PRECISION CONST. STORED AS IS.
0054 32 DSU A14 YES DT D - 151 153
0055 33 BDSU A14 YES DT D - 155 157 ----------------------------------------
0056 34 DAD A14 YES DT D - 161 163 RH OP: INDICATES THOSE CODES THAT SHOULD
0057 35 BE RIGHT-HAND OPERATORS, OR OTHERWISE
0058 36 DMP A14 YES DT D - 171 173 SHOULD BE ACCOMPANIED BY A BLANK RIGHT-
0059 *37 SETPD V NO - S - 175 --- HAND OPERATOR.
0060 40 CCLRB E+F NO - S B YES 065 067
R0061 GENERAL SHIFT CODES, SUFFIX 01 CODE 23. **** DEFINITION: ARC-CCS(X) = X + SGN(X)
# Annotation: in the listing "MODE" in the line below is crossed out, and "MODE IN;OUT" is written instead.
# The "MODE" column entries are modified:
# DT -> DT;-
# D -> DT;D
# V -> V;-
R0062 MODE UAL UAU IAL IAU ADAD OCT OCT* ADDRESS CODES
0064 0 SL DT -51 51 -177 177 20200 115 117 UAL -- UNINDEXED ADDRESS LOWER LIMIT
0066 1 SR DT -51 51 -177 177 20600 115 117 UAU -- UNINDEXED ADDRESS UPPER LIMIT
0068 2 SLR D -34 15 -177 177 21200 115 117 IAL -- INDEXED ADDRESS LOWER LIMIT
0070 3 SRR D -15 34 -177 177 21600 115 117 IAU -- INDEXED ADDRESS UPPER LIMIT
0072 4 VSL V -34 33 -177 177 20200 115 117 ADAD -- ADDITIVE FOR ADDRESS
0074 5 VSR V -33 34 -177 177 20600 115 117 FINISHED ADDRESS STORED LIKE A14 OR E.
# Page 19
# @AGC BLOCK II INTERPRETIVE CODES: ASSEMBLY RULES FOR AGC USER'S OWN PAGE NO. 2 PAGE 16
P0078 SUFFIX 10 CODES, NOT INDEXABLE.
R0079 ADDR MODE RH OCT ALTERNATE
R0080 TYPE OUT OP CODE SPELLING ADDRESS CODES
0082 00 AXT,2 C - 002 A ANY 15-BIT ADDRESS -- 0-52,
0084 01 AXT,1 C - 006 100-3777, 20000-167777. STORED
0086 02 AXC,2 C - 012 AS IS.
0088 03 AXC,1 C - 016
0090 04 LXA,2 E - 022
0091 05 LXA,1 E - 026 E ERASABLE -- 0-52, 100-3777.
0093 06 LXC,2 E - 032 STORED AS IS.
0095 07 LXC,1 E - 036
0096 10 SXA,2 E - 042 F FIXED -- 20000-167777. STORED
0098 11 SXA,1 E - 046 AS IS.
0100 12 XCHX,2 E - 052
0101 13 XCHX,1 E - 056
0102 14 INCR,2 C - 062 C CONSTANT -- ANY TYPE OF SINGLE-
0104 15 INCR,1 C - 066 PRECISION CONST. STORED AS IS.
0106 16 TIX,2 A - 072
0107 17 TIX,1 A - 076
0108 20 XAD,2 E - 102
0109 21 XAD,1 E - 106
0110 22 XSU,2 E - 112
0111 23 XSU,1 E - 116
0112 24 BZE A - 122
0113 25 GOTO A U YES 126 GO TO
0114 26 BPL A - 132
0115 27 BMN A - 136
0116 30 RTB F U 142
0117 31 BHIZ A - 146
0118 32 CALL A I YES 152
0119 33 STQ E - 156 ITA
0120 34 (SWITCH CODES)
0121 35
0122 36 BOVB F - 172
0123 37 BOV A - 176
012301*40 CALRB A B YES 152
R01231 MODES IN OPERAND MODES (FOR BEWARING END BANK) MODES OUT
R01232 - DON'T CARE D DOUBLE (2 WORDS) - NO CHANGE
R01233 D DOUBLE M MATRIX (18 WORDS) B UNKNOWN, REQUIRE BASIC INSTR. NEXT.
R01234 DT DOUBLE OR TRIPLE S SINGLE (1 WORD) D DOUBLE
R01235 V VECTOR T TRIPLE (3 WORDS) I UNKNOWN, REQUIRE INTERPRETIVE NEXT.
R01236 V VECTOR (6 WORDS) T TRIPLE
R01237 NOTE THAT FOR VXSC AND V/SC, U UNKNOWN
R01238 IF MODE IN = DT, OP MODE = V, AND IF MODE IN = U OR V, OP MODE = D. V VECTOR
# Page 20
# @AGC BLOCK II INTERPRETIVE CODES: ASSEMBLY RULES FOR AGC USER'S OWN PAGE NO. 3 PAGE 17
P0124 SWITCH CODES, SUFFIX 10 CODE 34.
R0125 ADDR MODE RH OCT ADDRESS ALTERNATE
R0126 TYPE OUT OP CODE ADDITIVE SPELLING ADDRESS CODES
0128 00 BONSET SW+A - 162 00000 A ANY 15-BIT ADDRESS -- 0-52,
0130 01 SETGO SW+A U YES 162 00020 100-3777, 20000-167777. STORED
0132 02 BOFSET SW+A - 162 00040 AS IS.
0134 03 SET SW - 162 00060
0136 04 BONINV SW+A - 162 00100 SW SWITCH BIT NUMBER -- 0-357.
0138 05 INVGO SW+A U YES 162 00120 STORED WITH SWITCH WORD NUMBER
0140 06 BOFINV SW+A - 162 00140 0-17 (THE INTEGER QUOTIENT OF
0142 07 INVERT SW - 162 00160 INV N/15) IN BITS 12-9 AND THE BIT-
0144 WITHIN-WORD NUMBER (00-16
0146 10 BONCLR SW+A - 162 00200 OCTAL, THE REMAINDER OF N/15)
0148 11 CLRGO SW+A U YES 162 00220 IN BITS 4-1. THIS IS THE ONLY
0150 12 BOFCLR SW+A - 162 00240 INSTANCE OF NUMBERING BITS FROM
0152 13 CLEAR SW - 162 00160 CLR LEFT TO RIGHT. 357 = 239D.
0154 14 BON SW+A - 162 00300
0155 16 BOFF SW+A - 162 00340 BOF
R0156 SUFFIX 000 CODES, UNARY OPERATIONS.
R0157 MODE MODE RH OCT ALTERNATE
R0158 IN OUT OP CODE SPELLING
0159 00 EXIT - B YES 000
0160 01 SQRT DT - 010
0161 02 SIN DT - 020 SINE
0162 03 COS DT - 030 COSINE
0163 04 ASIN DT - 040 ARCSIN
0164 05 ACOS DT - 050 ARCCOS
0165 06 DSQ DT - 060
0166 07 ROUND DT D 070
0167 10 DCOMP DT - 100
0168 11 VDEF DT V 110
0169 12 UNIT V - 120
0170 13 ABS DT - 130
0171 14 VSQ V D 140
0172 15 STADR - - YES 150
0173 16 RVQ - U YES 160 ITCQ IF QPRET POINTS TO ERASABLE, USE
0174 17 PUSH - - 170 GOTO QPRET , NOT RVQ.
0175 20 VCOMP V - 100
0176 23 ABVAL V D 130
# Page 21
# @AGC BLOCK II INTERPRETIVE CODES: ASSEMBLY RULES FOR AGC USER'S OWN PAGE NO. 4 PAGE 18
P0177 SUFFIX 100 CODES, SHORT SHIFT OPERATIONS.
# Annotation: in the listing, the table heading below is modified to change
# "MODE" to "MODE IN", and to add another column "MODE OUT".
R0178 MODE OCT CODE # Annotated entries:
# MODE IN MODE OUT
0179 00 SL1R D 004 # DT D
0180 01 SR1R D 014 # DT D
0181 02 SL1 DT 024 # DT -
0182 03 SR1 DT 034 # DT -
0183 04 SL2R D 044 # DT D
0184 05 SR2R D 054 # DT D
0185 06 SL2 DT 064 # DT -
0186 07 SR2 DT 074 # DT -
0187 10 SL3R D 104 # DT D
0188 11 SR3R D 114 # DT D
0189 12 SL3 DT 124 # DT -
0190 13 SR3 DT 134 # DT -
0101 14 SL4R D 144 # DT D
0192 15 SR4R D 154 # DT D
0193 16 SL4 DT 164 # DT -
0194 17 SR4 DT 174 # DT -
0195 20 VSL1 V 004 # V -
0196 21 VSR1 V 014 # V -
0197 22 VSL2 V 024 # V -
0198 23 VSR2 V 034 # V -
0199 24 VSL3 V 044 # V -
0200 25 VSR3 V 054 # V -
0201 26 VSL4 V 064 # V -
0202 27 VSR4 V 074 # V -
0203 30 VSL5 V 104 # V -
0204 31 VSR5 V 114 # V -
0205 32 VSL6 V 124 # V -
0206 33 VSR6 V 134 # V -
0207 34 VSL7 V 144 # V -
0208 35 VSR7 V 154 # V -
0209 36 VSL8 V 164 # V -
0210 37 VSR8 V 174 # V -
R0211 STORE CODES, ADDRESS CONSTANTS. COMPLEMENTED IF POSITIONED AS THE OPERAND OF A STADR CODE.
R0213 ADDR PUSH MODE OCTAL INDEX,1 INDEX,2 LOAD*
R0214 TYPE UP OUT CODE ADDITIVE ADDITIVE ADDITIVE ADDRESS CODES
0216 00-02 STORE E - - 00000 04000 10000 - A14 SEE SUFFIX 01 CODES.
0218 03-10 STODL E+A14 YES D 14000 - - 04000 A SEE SUFFIX 10 CODES.
0220 11-16 STOVL E+A14 YES V 24000 - - 04000 E SEE SUFFIX 10 CODES.
0222 17 STCALL E+A NO U 34000 - - -
# Page 22
# @AGC BLOCK II INTERPRETIVE CODES: ASSEMBLY RULES FOR AGC USER'S OWN PAGE NO. 5 PAGE 19
P0225 HOW TO PATCH INTERPRETIVE CODING FOR SIMULATIONS
R0226 ------------------------------------------------
R0227 PATCHING INTERPRETIVE CODING IS EASY IF YOU LIKE COMPLEMENTING, OCTAL DOUBLING, AND OCTAL HALVING. THE
R0229 OP CODES IN A WORD ARE FIRST INTERCHANGED, THEN INCREMENTED, THEN CONCATENATED INTO A WORD, WHICH IS FINALLY
R0231 COMPLEMENTED.
R0232 FOR INSTANCE, TO CONVERT VAD* VXSC INTO OCTAL:
R0233 FIRST LOOK UP THE OCTAL CODES: 123 015
R0234 AND INTERCHANGE THEM: 015 123
R0235 INCREMENT BOTH CODES: 016 124
R0236 SHIFT 016 LEFT 7 BITS: 01600 X 2 = 03400
R0236 ADD IN THE OTHER CODE: 03524
R0238 AND COMPLEMENT THE WHOLE SCHMIER: 74253
R0239 IF THERE IS JUST ONE OP CODE, IT IS ACCOMPANIED BY AN UNINCREMENTED ZERO. TO CONVERT RVQ INTO OCTAL:
R0241 LOOK UP THE OP CODE: 160
R0242 INCREMENT IT: 161
R0243 FORM THE WORD: 00161
R0244 AND COMPLEMENT IT: 77616
R0245 WHEN LOOKING UP OP CODES, BE CAREFUL NOT TO TAKE A BLK2 OP CODE FROM THE AGC LIST OR VICE VERSA. ***************
R0247 ADDRESS PECULIARITIES: ALL THE GENERAL SHIFT CODES HAVE THE SAME OCTAL CODE, 115 IF UNINDEXED OR 117
R0249 IF INDEXED. ALL THE SWITCH-BIT (FLAG) OPERATIONS USE OCTAL CODE 162. THE STORING OPERATIONS DON'T HAVE ANY OP
R0251 CODES AT ALL. IN THESE CASES THE OPERATION IS SPECIFIED BY AN ADDITIVE IN THE ADDRESS.
R0253 TO CONVERT AN ADDRESS 0 -5,2 THAT GOES WITH AN SRR* OP CODE:
R0254 LOOK UP THE ADDITIVE FOR SRR*: 21600
R0255 ADD IT TO THE ADDRESS VALUE: 21573
R0256 INCREMENT TO GET ARC-CCS FORM: 21574
R0257 SINCE INDEXED BY X2, COMPLEMENT:56203
R0258 TO FORM THE ADDRESS OF A FLAG BIT, YOU NEED THE FLAGWORD NUMBER (0-15D) AND THE RESIDUE MODULO 15 OF
R0260 THE FLAG NUMBER. THAT IS, THE FLAG NUMBER F IS RELATED TO THE FLAGWORD NUMBER W AND TO THE BIT NUMBER B BY THE
R0262 EQUATION F = 15W + (15 - B). TO CONVERT THE FLAG NUMBER 200D WITH THE OP CODE CLRGO:
R0264 DIVIDE 200D BY 15D TO GET W: 15 OCTAL
R0265 THE REMAINDER ( = 15 - B) IS 5 OCTAL (IF YOU STARTED WITH THE INFO W = 13, B = 10, JUST CONVERT 15 - B).
R0267 SHIFT W LEFT 8 BITS: 15000/2 = 6400
R0268 ADD 15 - B: 6405
R0269 ADDITIVE FOR CLRGO = 00220: 06625
R0270 TO CONVERT A STODL* WITH AN ADDRESS OF E5,1567:
R0271 CONVERT THE ADDRESS TO ECADR FORM:
R0272 SHIFT THE EBANK LEFT 8: 5000/2 = 2400
R0273 ADD REL. ADDRESS 1567 - 1400: 2567
R0274 STODL* ADDITIVE = 14000 + 4000: 22567
R0275 (IF FOLLOWS STADR, COMPLEMENT: 55210)
# Page 23
# @AGC BLOCK II INTERPRETIVE CODES: ASSEMBLY RULES FOR AGC USER'S OWN PAGE NO. 6 PAGE 20
P0276 OTHER INTERPRETIVE ADDRESSES ARE CADRS. TO MAKE A CADR FROM A PSEUDO-ADDRESS, SUBTRACT 10000. IF THE
R0278 RESULT IS OVER 77777 (BANKS 40-43), SUBTRACT 20000 MORE. TO CONVERT FBANK NOTATION INTO A CADR, REDUCE BANK 4X
R0280 TO THE CORRESPONDING 3X IF NECESSARY, SHIFT THE BANK NUMBER LEFT 10 BITS, SUBTRACT 2000 FROM THE SUBADDRESS, AND
R0282 ADD THE RESULTS. EXAMPLES:
R0283 (1) TO CONVERT 112233
R0284 SUBTRACT 10000: 102233
R0285 TOO BIG. SUBTRACT 20000: 62233
R0286 (2) TO CONVERT 41,3456
R0287 REDUCE BANK NUMBER INTO 30S: 31,3456
R0288 SHIFT BANK 10 LEFT: 31000 X 2 = 62000
R0289 ADD REL. ADDRESS = 3456 - 2000: 63456
