From 18569e85b3d63024d522b732f3a5694eda5f9110 Mon Sep 17 00:00:00 2001
From: Chuang-Yu Cheng <cycheng@multicorewareinc.com>
Date: Tue, 12 Apr 2016 03:10:52 +0000
Subject: [PATCH] [PPC64] Mark CR0 Live if PPCInstrInfo::optimizeCompareInstr
 Creates a Use of CR0

Resolve Bug 27046 (https://llvm.org/bugs/show_bug.cgi?id=27046).
The PPCInstrInfo::optimizeCompareInstr function could create a new use of
CR0, even if CR0 were previously dead. This patch marks CR0 live if a use of
CR0 is created.

Author: Tom Jablin (tjablin)
Reviewers: hfinkel kbarton cycheng

http://reviews.llvm.org/D18884

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@266040 91177308-0d34-0410-b5e6-96231b3b80d8
---
 lib/Target/PowerPC/PPCInstrInfo.cpp           |  4 ++++
 test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll | 23 +++++++++++++++++++++++
 2 files changed, 27 insertions(+)
 create mode 100644 test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 76f97b1..b6dc00f 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -1763,6 +1763,10 @@ bool PPCInstrInfo::optimizeCompareInstr(MachineInstr *CmpInstr,
           get(TargetOpcode::COPY), CRReg)
     .addReg(PPC::CR0, MIOpC != NewOpC ? RegState::Kill : 0);
 
+  // Even if CR0 register were dead before, it is alive now since the
+  // instruction we just built uses it.
+  MI->clearRegisterDeads(PPC::CR0);
+
   if (MIOpC != NewOpC) {
     // We need to be careful here: we're replacing one instruction with
     // another, and we need to make sure that we get all of the right
diff --git a/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
new file mode 100644
index 0000000..3c38209
--- /dev/null
+++ b/test/CodeGen/PowerPC/opt-cmp-inst-cr0-live.ll
@@ -0,0 +1,23 @@
+; RUN: llc -print-before=peephole-opts -print-after=peephole-opts -mtriple=powerpc64-unknown-linux-gnu -o /dev/null 2>&1 < %s | FileCheck %s
+
+define signext i32 @fn1(i32 %baz) {
+  %1 = mul nsw i32 %baz, 208
+  %2 = zext i32 %1 to i64
+  %3 = shl i64 %2, 48
+  %4 = ashr exact i64 %3, 48
+; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def,dead>;
+; CHECK: CMPLDI
+; CHECK: BCC
+
+; CHECK: ANDIo8 {{[^,]+}}, 65520, %CR0<imp-def>;
+; CHECK: COPY %CR0
+; CHECK: BCC
+  %5 = icmp eq i64 %4, 0
+  br i1 %5, label %foo, label %bar
+
+foo:
+  ret i32 1
+
+bar:
+  ret i32 0
+}
-- 
2.7.4