https://github.com/torvalds/linux
- HEAD
- refs/heads/arm64-uaccess
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/certifi-2024.7.4
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/idna-3.7
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/requests-2.32.2
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/setuptools-70.0.0
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/urllib3-2.2.2
- refs/heads/master
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Tip revision: 45a3e24f65e90a047bef86f927ebdc4c710edaa1 authored by Linus Torvalds on 18 June 2023, 21:06:27 UTC
Linux 6.4-rc7
Linux 6.4-rc7
Tip revision: 45a3e24
headsmp-scu.S
/* SPDX-License-Identifier: GPL-2.0+
*
* Shared SCU setup for mach-shmobile
*
* Copyright (C) 2012 Bastian Hecht
*/
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/memory.h>
/*
* Boot code for secondary CPUs.
*
* First we turn on L1 cache coherency for our CPU. Then we jump to
* secondary_startup that invalidates the cache and hands over control
* to the common ARM startup code.
*/
ENTRY(shmobile_boot_scu)
@ r0 = SCU base address
mrc p15, 0, r1, c0, c0, 5 @ read MPIDR
and r1, r1, #3 @ mask out cpu ID
lsl r1, r1, #3 @ we will shift by cpu_id * 8 bits
ldr r2, [r0, #8] @ SCU Power Status Register
mov r3, #3
lsl r3, r3, r1
bic r2, r2, r3 @ Clear bits of our CPU (Run Mode)
str r2, [r0, #8] @ write back
b secondary_startup
ENDPROC(shmobile_boot_scu)