https://github.com/torvalds/linux
- HEAD
- refs/heads/arm64-uaccess
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/certifi-2024.7.4
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/idna-3.7
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/requests-2.32.2
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/setuptools-70.0.0
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/urllib3-2.2.2
- refs/heads/master
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Tip revision: 9a351e30d72d409ec62c83f380e330e0baa584b4 authored by Linus Torvalds on 02 August 2005, 04:45:48 UTC
Linux v2.6.13-rc5
Linux v2.6.13-rc5
Tip revision: 9a351e3
ops-marvell.c
/*
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file "COPYING" in the main directory of this archive
* for more details.
*
* Copyright (C) 2003, 2004 Ralf Baechle (ralf@linux-mips.org)
*/
#include <linux/kernel.h>
#include <linux/types.h>
#include <linux/pci.h>
#include <asm/marvell.h>
static int mv_read_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 * val)
{
struct mv_pci_controller *mvbc = bus->sysdata;
unsigned long address_reg, data_reg;
u32 address;
address_reg = mvbc->config_addr;
data_reg = mvbc->config_vreg;
/* Accessing device 31 crashes those Marvells. Since years.
Will they ever make sane controllers ... */
if (PCI_SLOT(devfn) == 31)
return PCIBIOS_DEVICE_NOT_FOUND;
address = (bus->number << 16) | (devfn << 8) |
(where & 0xfc) | 0x80000000;
/* start the configuration cycle */
MV_WRITE(address_reg, address);
switch (size) {
case 1:
*val = MV_READ_8(data_reg + (where & 0x3));
break;
case 2:
*val = MV_READ_16(data_reg + (where & 0x3));
break;
case 4:
*val = MV_READ(data_reg);
break;
}
return PCIBIOS_SUCCESSFUL;
}
static int mv_write_config(struct pci_bus *bus, unsigned int devfn,
int where, int size, u32 val)
{
struct mv_pci_controller *mvbc = bus->sysdata;
unsigned long address_reg, data_reg;
u32 address;
address_reg = mvbc->config_addr;
data_reg = mvbc->config_vreg;
/* Accessing device 31 crashes those Marvells. Since years.
Will they ever make sane controllers ... */
if (PCI_SLOT(devfn) == 31)
return PCIBIOS_DEVICE_NOT_FOUND;
address = (bus->number << 16) | (devfn << 8) |
(where & 0xfc) | 0x80000000;
/* start the configuration cycle */
MV_WRITE(address_reg, address);
switch (size) {
case 1:
MV_WRITE_8(data_reg + (where & 0x3), val);
break;
case 2:
MV_WRITE_16(data_reg + (where & 0x3), val);
break;
case 4:
MV_WRITE(data_reg, val);
break;
}
return PCIBIOS_SUCCESSFUL;
}
struct pci_ops mv_pci_ops = {
.read = mv_read_config,
.write = mv_write_config
};