https://github.com/torvalds/linux
- HEAD
- refs/heads/arm64-uaccess
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/certifi-2024.7.4
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/idna-3.7
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/requests-2.32.2
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/setuptools-70.0.0
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/urllib3-2.2.2
- refs/heads/master
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Tip revision: cfb92440ee71adcc2105b0890bb01ac3cddb8507 authored by Linus Torvalds on 20 February 2022, 21:07:20 UTC
Linux 5.17-rc5
Linux 5.17-rc5
Tip revision: cfb9244
owl-mux.c
// SPDX-License-Identifier: GPL-2.0+
//
// OWL mux clock driver
//
// Copyright (c) 2014 Actions Semi Inc.
// Author: David Liu <liuwei@actions-semi.com>
//
// Copyright (c) 2018 Linaro Ltd.
// Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
#include <linux/clk-provider.h>
#include <linux/regmap.h>
#include "owl-mux.h"
u8 owl_mux_helper_get_parent(const struct owl_clk_common *common,
const struct owl_mux_hw *mux_hw)
{
u32 reg;
u8 parent;
regmap_read(common->regmap, mux_hw->reg, ®);
parent = reg >> mux_hw->shift;
parent &= BIT(mux_hw->width) - 1;
return parent;
}
static u8 owl_mux_get_parent(struct clk_hw *hw)
{
struct owl_mux *mux = hw_to_owl_mux(hw);
return owl_mux_helper_get_parent(&mux->common, &mux->mux_hw);
}
int owl_mux_helper_set_parent(const struct owl_clk_common *common,
struct owl_mux_hw *mux_hw, u8 index)
{
u32 reg;
regmap_read(common->regmap, mux_hw->reg, ®);
reg &= ~GENMASK(mux_hw->width + mux_hw->shift - 1, mux_hw->shift);
regmap_write(common->regmap, mux_hw->reg,
reg | (index << mux_hw->shift));
return 0;
}
static int owl_mux_set_parent(struct clk_hw *hw, u8 index)
{
struct owl_mux *mux = hw_to_owl_mux(hw);
return owl_mux_helper_set_parent(&mux->common, &mux->mux_hw, index);
}
const struct clk_ops owl_mux_ops = {
.get_parent = owl_mux_get_parent,
.set_parent = owl_mux_set_parent,
.determine_rate = __clk_mux_determine_rate,
};