https://github.com/torvalds/linux
- HEAD
- refs/heads/arm64-uaccess
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/certifi-2024.7.4
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/idna-3.7
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/requests-2.32.2
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/setuptools-70.0.0
- refs/heads/dependabot/pip/drivers/gpu/drm/ci/xfails/urllib3-2.2.2
- refs/heads/master
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Tip revision: fc74e0a40e4f9fd0468e34045b0c45bba11dcbb2 authored by Linus Torvalds on 26 December 2021, 21:17:17 UTC
Linux 5.16-rc7
Linux 5.16-rc7
Tip revision: fc74e0a
qcom,dispcc-sc7180.h
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2019, The Linux Foundation. All rights reserved.
*/
#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SC7180_H
#define DISP_CC_PLL0 0
#define DISP_CC_PLL0_OUT_EVEN 1
#define DISP_CC_MDSS_AHB_CLK 2
#define DISP_CC_MDSS_AHB_CLK_SRC 3
#define DISP_CC_MDSS_BYTE0_CLK 4
#define DISP_CC_MDSS_BYTE0_CLK_SRC 5
#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 6
#define DISP_CC_MDSS_BYTE0_INTF_CLK 7
#define DISP_CC_MDSS_DP_AUX_CLK 8
#define DISP_CC_MDSS_DP_AUX_CLK_SRC 9
#define DISP_CC_MDSS_DP_CRYPTO_CLK 10
#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC 11
#define DISP_CC_MDSS_DP_LINK_CLK 12
#define DISP_CC_MDSS_DP_LINK_CLK_SRC 13
#define DISP_CC_MDSS_DP_LINK_DIV_CLK_SRC 14
#define DISP_CC_MDSS_DP_LINK_INTF_CLK 15
#define DISP_CC_MDSS_DP_PIXEL_CLK 16
#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC 17
#define DISP_CC_MDSS_ESC0_CLK 18
#define DISP_CC_MDSS_ESC0_CLK_SRC 19
#define DISP_CC_MDSS_MDP_CLK 20
#define DISP_CC_MDSS_MDP_CLK_SRC 21
#define DISP_CC_MDSS_MDP_LUT_CLK 22
#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 23
#define DISP_CC_MDSS_PCLK0_CLK 24
#define DISP_CC_MDSS_PCLK0_CLK_SRC 25
#define DISP_CC_MDSS_ROT_CLK 26
#define DISP_CC_MDSS_ROT_CLK_SRC 27
#define DISP_CC_MDSS_RSCC_AHB_CLK 28
#define DISP_CC_MDSS_RSCC_VSYNC_CLK 29
#define DISP_CC_MDSS_VSYNC_CLK 30
#define DISP_CC_MDSS_VSYNC_CLK_SRC 31
#define DISP_CC_XO_CLK 32
/* DISP_CC GDSCR */
#define MDSS_GDSC 0
#endif