\begin{sidewaystable}
\begin{center}
\caption{Main parameters of the simulated cores.}
\label{tab:sim-params}
\begin{threeparttable}[b]
\begin{tabular}{|ll|c|c|c|} \hline
\multicolumn{2}{|c|}{Parameter}                                                      & Single-issue            & Dual-issue              & Triple-issue     \\ \hline
\multicolumn{2}{|l|}{Pipeline type}                                                  & IO only           & IO or OOO& IO or OOO \\ \hline
\multicolumn{2}{|l|}{Core clock}                                                     & 1.4~GHz                 & 1.6~GHz                 & 2.0~GHz          \\ \hline
\monocol{|l|}{DRAM}                         & Size/clock/latency (ns)            & 256~MB/933~MHz/81   & 256~MB/933~MHz/81   & 256~MB/933~MHz/81  \\ \hline
\monocol{|l|}{L2}                           & Size/assoc./lat./MSHRs/WBs     & 512~kB/8/3/8/16 & 1024~kB/8/5/8/16& 2048~kB/16/8/11/16 \\ \hline
\monocol{|l|}{L1-I}                         & Size/assoc./lat./MSHRs           & 32~kB/2/1/2       & 32~kB/2/1/2       & 32~kB/2/1/2      \\ \hline
\monocol{|l|}{L1-D}                         & Size/assoc./lat./MSHRs/WBs     & 32~kB/4/1/4/4   & 32~kB/4/1/5/8   & 32~kB/2/1/6/16   \\ \hline
\monocol{|l|}{Stride prefet.}               & Cache level/degree/buffer size     & 1/1/8               & 1/1/12              & 2/1/16                \\ \hline
\monocol{|l|}{\multirow{2}{*}{Branch pred.}}& Global/local history entries (bits)  & 256 (2)/-           & 4096 (2)/-          & 4096 (2)/1024 (3)  \\ \cline{2-5}
\monocol{|c|}{}                             & BTB/RAS entries                      & 256/8                 & 4096/16               & 4096/48        \\ \hline
\multicolumn{2}{|l|}{Front\hyp{}end/back\hyp{}end width}                                     & 1/1                   & 2/4                   & 3/7              \\ \hline
\multicolumn{2}{|l|}{INT/FP pipeline depth (+ extra OOO stages)}          & 8/10                  & 8/12 (+3)             & 9/18 (+6)            \\ \hline
\multicolumn{2}{|l|}{Physical INT/FP registers\tnote{2}}            & -                     & 82/256                & 90/256           \\ \hline
\multicolumn{2}{|l|}{ITLB/DTLB/IQ/LSQ/ROB\tnote{2}\,\, entries}                    & 32/32/16/8~each/-     & 64/64/32/12~each/40   & 128/128/48/16~each/60 \\ \hline
\monocol{|l|}{\multirow{2}{*}{INT units}}   & ALU/MUL execution ports              & 1/1                   & 2/1                   & 2/1             \\ \cline{2-5}
\monocol{|c|}{}                             & ADD/MUL cycles                       & 1/4                   & 1/4                   & 1/4             \\ \hline
\monocol{|l|}{\multirow{2}{*}{FP/SIMD}}     & Execution ports                        & 1                       & 1 or 2                  & 1, 2 or 3         \\ \cline{2-5}
\monocol{|c|}{}                             & VADD/VMUL/VMLA cycles              & 3/4/6               & 4/5/8               & 10/12/20      \\ \hline
\monocol{|l|}{\multirow{2}{*}{Load/store}}  & Execution ports                        & 1 shared                & 1 shared                & 1 for each        \\ \cline{2-5}
\monocol{|c|}{}                             & Load/store cycles                    & 1/1                   & 2/1                   & 3/2             \\ \hline
\end{tabular}
\begin{tablenotes}
    \item [1] Over-dimensioned to compensate the lack of L2-TLB.
    \item [2] For \ooo{} only.
\end{tablenotes}
\end{threeparttable}
\end{center}
\end{sidewaystable}