| 3dd3292 | John Linn | 25 August 2010, 21:08:19 UTC | Merge branch 'pele-peep5' into pele-alpha2 Resolved Conflicts: arch/arm/configs/xilinx_defconfig | 25 August 2010, 21:08:19 UTC |
| 8a0431a | John Linn | 25 August 2010, 19:35:40 UTC | Xilinx: ARM: Adding L2 cache to defconfigs for PEEP5 PEEP4 had problems with the L2 cache on. This enables L2 cache as we're seeing good results with PEEP5. | 25 August 2010, 19:35:40 UTC |
| 67d1351 | Naveen Mamindlapalli | 25 August 2010, 18:16:37 UTC | Xilinx: MTD Subsystem workaround for HZ=20. This is the work around for HZ value of 20. Otherwise the delays won't work. Signed-off-by: Naveen naveenm@xilinx.com | 25 August 2010, 19:29:50 UTC |
| 986d985 | Naveen Mamindlapalli | 25 August 2010, 16:04:15 UTC | Xilinx: SMC NAND Controller driver Added the SMC NAND controller driver code into the linux kernel. Signed-off-by: Naveen naveenm@xilinx.com | 25 August 2010, 19:29:45 UTC |
| 2dda69a | Naveen Mamindlapalli | 25 August 2010, 16:01:22 UTC | Xilinx: SMC NAND Definitions Added the SMC NAND controller definitions to the device list. Signed-off-by: Naveen naveenm@xilinx.com | 25 August 2010, 19:29:39 UTC |
| 8432b3b | John Linn | 24 August 2010, 21:02:30 UTC | Xilinx: ARM: Updated kernel default configs for automated testing The automated testing is moved to use NFS root such that the kernel command line has to be changed. | 24 August 2010, 21:10:37 UTC |
| 6aee319 | John Linn | 23 August 2010, 20:59:14 UTC | Xilinx: ARM: Update defconfigs to include PSS WDT Both WDTs can't be in the kernel at the same time right now so only the PSS WDT is on be default. | 23 August 2010, 20:59:14 UTC |
| dd0507e | John Linn | 20 August 2010, 23:16:30 UTC | Merge branch 'pele-peep4' of /home/linnj/linux_arm/devel/linux-2.6-xlnx-peep4-debug into pele-peep4 | 20 August 2010, 23:16:30 UTC |
| 236e029 | John Linn | 20 August 2010, 22:40:36 UTC | Xilinx: ARM: GEM: removed debug output The driver had debug turned on that dumped all the phy registers when the ifconfig was done. This turns it off. | 20 August 2010, 22:48:12 UTC |
| 01d0ca0 | John Linn | 20 August 2010, 19:48:01 UTC | Xilinx: ARM: Updated defconfigs for ramdisk size Changed to allow a 16 MB ramdisk. | 20 August 2010, 19:48:01 UTC |
| 9402a99 | John Linn | 20 August 2010, 18:05:25 UTC | Merge branch 'pele-peep4' of /home/linnj/linux_arm/devel/linux-2.6-xlnx-peep4-debug into pele-peep4 | 20 August 2010, 18:05:25 UTC |
| e59be83 | John Linn | 20 August 2010, 17:41:34 UTC | Xilinx: ARM: Updating def configs, removed some, added some The defconfigs had got confusing, trying to reduce them some and clarify which ones to use for the alpha. Use xilinx_defconfig for non-SMP, and xilinx_smp_defconfig for SMP. | 20 August 2010, 17:41:34 UTC |
| b50702c | Sadanand | 20 August 2010, 06:15:45 UTC | Xilinx: ARM: Watchdog drivers: Fix compiler errors and update clks This patch fixes compiler errors in the SCU WDT driver and updates the clock frequencies for the SCU WDT and PSS WDT. These drivers have been tested on PEEP4 Signed-off-by: Sadanand M <sadanan@xilinx.com> | 20 August 2010, 15:18:16 UTC |
| 9147a81 | John Linn | 20 August 2010, 00:07:58 UTC | Xilinx: ARM: Updated SMP boot so kernel writes CPU1 reset vector To make it easier without u-boot for SMP booting, like with jtag, the kernel now writes the CPU1 reset vector. This also keeps all the hacky code together in the kernel as u-boot changes are not required at all for booting SMP kernel. | 20 August 2010, 00:07:58 UTC |
| 0be24f9 | John Linn | 19 August 2010, 23:05:19 UTC | Xilinx: ARM: Update SMP boot to work with u-boot and boot rom New code was added to reset CPU1 to get CPU1 out of the wfe state that the boot rom put it into. This assumes that u-boot or something like jtag_tcl has put a branch to 0x8000 in address 0 so that CPU1 has a boot vector to get to the kernel. Without u-boot, a 0xE3a0F902 can be written into address 0 so that the reset of CPU1 will work. | 19 August 2010, 23:05:19 UTC |
| cf943e7 | Brian Hill | 17 August 2010, 15:16:20 UTC | Xilinx: ARM: Restructure the GEM NAPI poll implementation. | 17 August 2010, 15:16:20 UTC |
| bdbf97e | Brian Hill | 17 August 2010, 13:59:42 UTC | Merge branch 'pele-peep4' of git://git-dev.xilinx.com/linux-2.6-xlnx into pele-peep4 | 17 August 2010, 13:59:42 UTC |
| 890c845 | Brian Hill | 17 August 2010, 13:59:11 UTC | Xilinx: ARM: Convert GEM RX operation to not copy packet data. RX data DMAd directly into waiting preallocated SKB buffer. | 17 August 2010, 13:59:11 UTC |
| 1f9b08b | John Linn | 13 August 2010, 18:20:17 UTC | Merge branch 'pele-peep4' of /home/linnj/linux_arm/devel/linux-2.6-xlnx-peep2.1 into pele-peep4 | 13 August 2010, 18:20:17 UTC |
| 5bba3d5 | John Linn | 13 August 2010, 18:16:53 UTC | Revert "Revert "Xilinx: ARM: removing DMA from the test temporarily"" This reverts commit 32334031a99caeeec395f7ab40a7a22bd6067197. DMA still not working reliably in automation, removing it again. | 13 August 2010, 18:16:53 UTC |
| b3e45d9 | Brian Hill | 12 August 2010, 20:19:42 UTC | Xilinx: ARM: Remove extraneous error output message when GEM TX ring full. | 12 August 2010, 20:19:42 UTC |
| 76efb2a | Brian Hill | 12 August 2010, 16:39:04 UTC | Xilinx: ARM: Correct GEM descriptor ring handling. | 12 August 2010, 16:39:04 UTC |
| d921057 | John Linn | 12 August 2010, 15:43:32 UTC | Xilinx: ARM: updating u-boot image This image is based on a build from git-dev for peep4. | 12 August 2010, 15:43:32 UTC |
| 7602f63 | John Linn | 11 August 2010, 22:31:42 UTC | Xilinx: ARM: PSS WDT: Corrected the device address for PEEP4 The address being used was an old address which caused the kernel to crash. | 11 August 2010, 22:31:42 UTC |
| 74f6a64 | John Linn | 11 August 2010, 21:22:55 UTC | Xilinx: ARM: PSS WDT: Updated driver so it will compile Apparently it wasn't including the right header files and was relying on some other header to include slab.h and that header no longer does so it wouldn't compile. This updates it to include slab.h. | 11 August 2010, 21:22:55 UTC |
| 4b80581 | Haibing Ma | 09 August 2010, 16:10:34 UTC | Xilinx: ARM: DMA: 1 8-channel DMAC Changed the pl330 driver and devices.c so it has 1 8-channel DMAC changed the irq numbers accordingly Changed the test so the expected error code matches the the actual one Signed-off-by: Haibing Ma <haibing.ma@xilinx.com> | 09 August 2010, 21:55:45 UTC |
| 3233403 | John Linn | 09 August 2010, 21:54:26 UTC | Revert "Xilinx: ARM: removing DMA from the test temporarily" This reverts commit 081d803be9df4da5c404610520f42c2a3976ffa2. | 09 August 2010, 21:54:26 UTC |
| 2f11c9b | John Linn | 06 August 2010, 21:21:16 UTC | Xilinx: ARM: Updating test defconfig for NOR/MTD This config now has MTD, NOR drivers, and a bigger ram disk for the new test. | 06 August 2010, 21:21:16 UTC |
| 081d803 | John Linn | 05 August 2010, 21:30:18 UTC | Xilinx: ARM: removing DMA from the test temporarily The test is failing in Peep4 and it's easiest to remove it til it's working. This commit can be reverted later to put it back in. | 05 August 2010, 21:30:18 UTC |
| debceab | John Linn | 05 August 2010, 21:28:58 UTC | Xilinx: ARM: Updated I2C eeprom address for Peep4 The I2C eeprom moved addresses on the I2C bus again in Peep4. | 05 August 2010, 21:28:58 UTC |
| 28716c6 | John Linn | 04 August 2010, 19:50:46 UTC | Xilinx: ARM: updated u-boot binary for PEEP4 design Some addresses were changed and a new binary is needed. | 04 August 2010, 19:50:46 UTC |
| 78e2b26 | John Linn | 04 August 2010, 14:20:35 UTC | Xilinx: ARM: Added new tcl file for PEEP4 initialization The new file, remap_ddr_peep4.tcl, remaps DDR to 0 and also adds a new register that is in PEEP4 to map ram up high. This script should be sourced before runnning u-boot or Linux. | 04 August 2010, 14:20:35 UTC |
| e889991 | John Linn | 03 August 2010, 23:00:29 UTC | Xilinx: ARM: fixed SMP for PEEP4 The 2nd CPU was not coming up quick enough for the 1 HZ timout so this changed that timeout to be 3 * HZ. | 03 August 2010, 23:00:29 UTC |
| d898c14 | John Linn | 02 August 2010, 20:06:10 UTC | Xilinx: ARM: Updating addresses for PEEP4 design Some of the addresses moved as PEEP4 is RTL 2.5 and matches architecture spec version 1.2 | 02 August 2010, 20:06:10 UTC |
| ac59f71 | John Linn | 22 July 2010, 16:19:05 UTC | Xilinx: ARM: MTD: fixing CFI for Numonyx CFI bug The M29EW devices seem to report the CFI information wrong when it's in 8 bit mode. There's an app note from Numonyx on this issue and there's a patch in the open source, but it doesn't seem to be in the mainline. This commit is based on that patch from Massimo Cirillo titled: buffer size adjustment for M29EW Numonyx devices. | 22 July 2010, 16:19:05 UTC |
| 2ec4e8d | John Linn | 20 July 2010, 16:33:10 UTC | Xilinx: ARM: Adding new kernel def config for PEEP This defconfig is aimed to be the default for PEEP. The may also be a specific defconfig for a design, such as PEEP2 if required. | 20 July 2010, 16:33:10 UTC |
| a6937a9 | sadanan | 20 July 2010, 10:33:29 UTC | Xilinx: ARM: Removed xnorpss.c driver and moved SMC init code to xilinx.c Users can use the physmap.c driver with the nor flash in PSS. This patch has been tested on peep3, using the mtd utilities. Signed-off-by: Sadanand M <sadanan@xilinx.com> | 20 July 2010, 13:53:41 UTC |
| e53d823 | John Linn | 19 July 2010, 15:15:43 UTC | Xilinx: ARM: Updated u-boot.pele image to work with PEEP3 and GEM u-boot is now working with GEM with BRAM. This image will let you download a kernel such that development time should be reduced. | 19 July 2010, 15:15:43 UTC |
| 900893b | John Linn | 17 July 2010, 21:37:58 UTC | Xilinx: ARM: Updated NOR flash base address and init for PEEP / EP107 The register initialization changed for the SMC controller on PEEP and the base address of flash also moved from the 1st one to the 2nd. | 17 July 2010, 21:37:58 UTC |
| 6aaef94 | John Linn | 17 July 2010, 21:35:55 UTC | Xilinx: ARM: Updated SPI to slow down the SPI eeprom frequency The eeprom didn't seem to work at the 5 MHz so I slowed down to 1 MHz. | 17 July 2010, 21:35:55 UTC |
| b4f8562 | John Linn | 17 July 2010, 21:29:40 UTC | Xilinx: ARM: Updated EMAC PHY address for PEEP design on EP107 The PHY changed from 0x7 to 0x17. | 17 July 2010, 21:29:40 UTC |
| 8eca225 | John Linn | 07 July 2010, 20:05:05 UTC | Xilinx: ARM: Adding new tcl script, linuxsmp-peep3.tcl, for peep3 The address map changed in PEEP3 since it's RTL 2 which moved the address for the device configuration registers. | 07 July 2010, 20:07:22 UTC |
| e49aef5 | John Linn | 01 July 2010, 16:10:00 UTC | Xilinx: ARM: Changed Makefile to run convert script In order to make it easier for users, the script to convert the vmlinux file is now ran automatically. This will be removed when we start using the bootstrap loader with the kernel (uncompressor). | 01 July 2010, 16:10:00 UTC |
| b9807f0 | John Linn | 29 June 2010, 18:14:47 UTC | Xilinx: ARM: removed Peep linux tcl to force smp testing I removed linux.tcl so that linuxsmp.tcl would be used. | 29 June 2010, 18:14:47 UTC |
| a7380b8 | John Linn | 29 June 2010, 17:53:31 UTC | Xilinx: ARM: Moving peep2 config to be SMP by default The smp defconfig is now removed so that all peep testing will be using the smp kernel. SMP can be disabled in the kernel config if there's any issues. | 29 June 2010, 17:53:31 UTC |
| d23f054 | John Linn | 29 June 2010, 17:51:44 UTC | Xilinx: ARM: Added V6K back into config CPU_V6K was turned off with SMP just do to debugging. This turns it back on since the processor supports those instructions. | 29 June 2010, 17:51:44 UTC |
| c746f02 | John Linn | 28 June 2010, 20:44:01 UTC | Xilinx: ARM: SMP updates for local timers This removes all hacks that were in and arch/arm/kernel/smp.c now matches the code in the mainline 2.6.34. Local timers are now working. | 28 June 2010, 20:44:01 UTC |
| 58ff96b | John Linn | 28 June 2010, 19:20:03 UTC | Xilinx: ARM: Updated TCL scripts for loading and compressed ramdisk The TCL scripts were updated to load the new compressed ramdisk to help minimize the download time of the ramdisk until ethernet is working on PEEP. | 28 June 2010, 19:20:03 UTC |
| ee9524f | John Linn | 28 June 2010, 14:32:32 UTC | Xilinx: ARM: fixing broadcast timer device when no local timers The initialization of percpu timers was commented out during previous local timer testing, but this won't work for when local timers are disabled. The broadcast method when local timers are disabled require this initialization. This appears to fix the timing problems I was seeing in the SMP mode with processes on CPU1 not working with any time requirements. The sleep command and top both work now on on CPUs. | 28 June 2010, 14:32:32 UTC |
| 5fcc463 | John Linn | 24 June 2010, 20:54:41 UTC | Merge branch 'pele-peep2' of /home/bhill/pele/linux-2.6-xlnx into pele-peep2-l2cache | 24 June 2010, 20:54:41 UTC |
| 9aadd99 | Jason McMullan | 05 May 2010, 17:59:37 UTC | ARM: 6094/1: Extend cache-l2x0 to support the 16-way PL310 The L310 cache controller's interface is almost identical to the L210. One major difference is that the PL310 can have up to 16 ways. This change uses the cache's part ID and the Associativity bits in the AUX_CTRL register to determine the number of ways. Also, this version prints out the CACHE_ID and AUX_CTRL registers. Acked-by: Will Deacon <will.deacon@arm.com> Acked-by: Acked-by: Catalin Marinas <catalin.marinas@arm.com> Signed-off-by: Jason S. McMullan <jason.mcmullan@netronome.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> | 24 June 2010, 20:52:56 UTC |
| a756245 | Brian Hill | 24 June 2010, 20:46:09 UTC | Xilinx: ARM: Add PL310 L2CC support to PEEP2 build. | 24 June 2010, 20:46:09 UTC |
| de7bb75 | John Linn | 22 June 2010, 22:54:02 UTC | Merge branch 'master' into pele-peep2-34 Resolved Conflicts: arch/arm/Kconfig arch/arm/mm/Kconfig drivers/gpio/Makefile drivers/i2c/busses/Kconfig drivers/i2c/busses/Makefile drivers/watchdog/Kconfig drivers/watchdog/Makefile | 22 June 2010, 22:54:02 UTC |
| 13d428e | John Linn | 22 June 2010, 18:14:33 UTC | Xilinx: ARM: Adding tcl to load the PEEP easier There are a couple things that have to be done before loading the kernel and it's easier to do that in tcl. This includes making the on board ram visible at low and high addresses rather than ROM and mapping DDR down to address 0. Once in TCL, source the scripts to load the kernel and ramdisk. | 22 June 2010, 18:14:33 UTC |
| 440ee16 | John Linn | 22 June 2010, 18:06:19 UTC | Xilinx: ARM: Updated defconfigs for PEEP2, SMP and non-SMP Removed the EP107 defconfig as that name is not clear. Now moving to using the PEEP name which should be clearer. | 22 June 2010, 18:06:19 UTC |
| 543353a | John Linn | 21 June 2010, 23:28:04 UTC | Xilinx: ARM: Updated SMP boot processing to remove hacks This change cleans up the SMP boot processing and makes it closely match what it should be based on the ARM model. It does still incorporate some code that should be moved to a boot loader. It now uses fixed addresses for the handshaking to the boot loader code with 2 addresses, one for the address to jump to from the boot loader, and another to signal when CPU0 is ready for CPU1 to start the kernel. | 22 June 2010, 17:57:34 UTC |
| 232ab69 | John Linn | 19 June 2010, 15:58:56 UTC | Xilinx: ARM: Prevent timer warnings due to local timers not working This commit adds conditional compilation to the smp code around the percpu_timer_init calls so that when local times are disabled, these functions don't get called. Without this, the timer was giving warnings when the kernel booted that indicated the clockevents could not switch to one-shot mode: dummy timer is not functional. Once local timers are fixed, this code should be removed. | 19 June 2010, 15:58:56 UTC |
| 352a1a8 | John Linn | 19 June 2010, 15:21:31 UTC | Xilinx: ARM: Fixing SMP boot on PEEP2 The method used for SMP boot on Palladium didn't work correctly on PEEP2. When CPU1 was polling for the boot key it seemed to stop CPU0 from executing the kernel almost like it was being starved of any throughput on the bus. A WFE is added to head.S for putting CPU1 into a sleep mode so that it isn't hogging the bus and CPU0 can boot. It was also necessary to put an sev instruction into smp.c for CPU0 to wakeup CPU1, but onluy after writing the key into the boot lock and flushing the caches. Note it was necessary to put the WFE in CPU1 code in the loop that checks the boot lock for the key because debug events (most commands in the JTAG TCL) cause the WFE to wakeup falsely. It's also necessary for CPU1 to write the key and flush BEFORE doing the sev instruction. | 19 June 2010, 15:21:31 UTC |
| 0fbd949 | John Linn | 19 June 2010, 15:17:45 UTC | Xilinx: ARM: Updating TTC input clock rate for PEEP2 The input clock is faster so it needs to match the hardware. Prior to this change the bogoMIPS from the kernel was very low, now it is more matching the previous DF platform. | 19 June 2010, 15:17:45 UTC |
| a0d4b63 | John Linn | 19 June 2010, 15:11:52 UTC | Xilinx: ARM: Moving the kernel back to address 0 for PEEP2 We figured out the issue with DDR such that now it can be mapped to 0 such that the kernel can be mapped at 0. Mapping it at 0 is easier because it's a direct mapping between virtual and physical (mask the top nibble from a virtual to get a physical) which makes it easier to deal with in code. The SMP code broke when the kernel was moved to 0x208000 because the key address virtual to physical was no longer a direct mapping. The following TCL commands should be used prior to loading the kernel on the PEEP2 design so that DDR is mapped at 0, otherwise the kernel loading will cause an error when it's most of the way loaded. mwr 0xfef00000 0 mwr 0xfef00040 0 mwr 0xfef00000 0x2 | 19 June 2010, 15:11:52 UTC |
| 47ccc5d | John Linn | 17 June 2010, 18:53:14 UTC | Xilinx: ARM: Updating to use A9 local timer This commit is not working all the way yet. The irq is working, but the kernel is locking up at aio_setup, add init_debug to kernel command line. | 17 June 2010, 19:57:14 UTC |
| 31137b4 | John Linn | 09 June 2010, 21:21:20 UTC | Xilinx: ARM: Changed i2c eeprom to match new PEEP (EP-107) The new board has a different eeprom on the i2c bus. It has been tested in a limited way and is working. | 09 June 2010, 21:21:20 UTC |
| 5ae34f9 | John Linn | 09 June 2010, 21:19:25 UTC | Xilinx: ARM: Updated hardware.h to increase memory Increased from 23 to 128 Meg thinking it might help the kernel be faster on the new PEEP. Didn't help that, but seems useful anyway now that there's more testing on network builds. | 09 June 2010, 21:19:25 UTC |
| 1b30409 | John Linn | 08 June 2010, 16:09:05 UTC | Xilinx: ARM: Adding new defconfig for the new PEEP board (EP107) For the transition from the Dragonfire EP platform to the new PEEP platform referred to as EP107, this should make it clearer. It can go away at some point soon. The new file, xilinx_ep107_defconfig, also minimizes the kernel size right now as the platform is really slow. All kernel debug is turned off to try to help speed it up. | 08 June 2010, 16:10:45 UTC |
| e1605e7 | John Linn | 08 June 2010, 16:06:47 UTC | Merge branch 'pele' into pele-ep107-new | 08 June 2010, 16:06:47 UTC |
| 91e2c43 | John Linn | 08 April 2010, 16:19:47 UTC | Add non-Virtex5 support for LL TEMAC driver This patch adds support for using the LL TEMAC Ethernet driver on non-Virtex 5 platforms by adding support for accessing the Soft DMA registers as if they were memory mapped instead of solely through the DCR's (available on the Virtex 5). The patch also updates the driver so that it runs on the MicroBlaze. The changes were tested on the PowerPC 440, PowerPC 405, and the MicroBlaze platforms. Signed-off-by: John Tyner <jtyner@cs.ucr.edu> Signed-off-by: John Linn <john.linn@xilinx.com> | 08 June 2010, 14:57:03 UTC |
| 2ef76f8 | John Linn | 07 June 2010, 22:00:41 UTC | Xilinx: ARM: Move the kernel from 0 to 0x200000 On the EP107, there were problems with the kernel at 0 as it is in both onboard ram and DDR. This moves it to be totally in DDR. | 08 June 2010, 14:34:59 UTC |
| c465251 | John Linn | 07 June 2010, 21:01:12 UTC | Xilinx: ARM: Adding ability to run kernel on CPU1 This change adds the ability to setup CPU1 to run the kernel while nothing is running on CPU0. A menu is added under the Xilinx platform to select it and the GIC is updated to set irqs to be on CPU1. | 08 June 2010, 14:34:40 UTC |
| c42994b | John Linn | 07 June 2010, 20:53:41 UTC | Xilinx: ARM: Fix to allow kernel to run on CPU1 The SMP code that was added didn't only affect SMP, but AMP when trying to run the kernel only on CPU1. This change just prevents CPU1 from getting stuck in the loop at the front of head which is designed to catch CPU1 when running SMP. | 07 June 2010, 22:15:38 UTC |
| 61bec8b | John Linn | 02 June 2010, 23:20:12 UTC | Xilinx: ARM: Added the ability to disable the D cache The kernel always had a config option, but I think the kernel didn't build. This disables the ldrex/strex instructions so the kernel builds and runs. This can't be used with SMP. | 07 June 2010, 21:21:45 UTC |
| 56d91fe | John Linn | 03 June 2010, 23:24:56 UTC | Xilinx: ARM: Adding tar file for nfs root file system This new tar file can be untarred onto a network drive and then used for nfs root. | 04 June 2010, 20:27:55 UTC |
| cc95a70 | John Linn | 03 June 2010, 23:04:51 UTC | Xilinx: ARM: Added def config file for nfs root This def config file has the command line setup correctly to allow nfs root to be used to boot the kernel. It also has D cache disabled since the network is working ok without it on. | 03 June 2010, 23:04:51 UTC |
| bcd7a30 | John Linn | 03 June 2010, 23:03:00 UTC | Xilinx: ARM: Updated the network defconfig Disabled the D cache for now as the network is working better now if it's disabled. | 03 June 2010, 23:03:00 UTC |
| 944dbf5 | John Linn | 02 June 2010, 23:20:12 UTC | Xilinx: ARM: Added the ability to disable the D cache The kernel always had a config option, but I think the kernel didn't build. This disables the ldrex/strex instructions so the kernel builds and runs. This can't be used with SMP. | 02 June 2010, 23:20:12 UTC |
| c5b2b35 | John Linn | 02 June 2010, 22:36:50 UTC | Xilinx: ARM: GEM: Fixed bug with tx used bit Fixed a bug where the tx used bit was not being checked by the driver. Also removed a lot of debug output. | 02 June 2010, 22:42:12 UTC |
| 4bcaa22 | John Linn | 02 June 2010, 18:09:50 UTC | Merge branch 'master-lltemac-tuning' of ../../../linux_mb/devel/linux-2.6-xlnx into master-lltemac-tuning | 02 June 2010, 18:09:50 UTC |
| 97b5d26 | Michal Simek | 10 May 2010, 10:09:43 UTC | ll_temac: Fix mtu change function when device is not open xenet_change_mtu doesn't take care about current device state. Adding checking mechanism about currect device state solve it. Replicate this error: ifconfig eth0 down ifconfig eth0 mtu 2000 Signed-off-by: Michal Simek <monstr@monstr.eu> | 02 June 2010, 18:07:21 UTC |
| 6419f68 | Michal Simek | 04 May 2010, 14:43:30 UTC | ll_temac: Allocate skb buffer which correspond to mtu size + pad This patch fix regression on Microblaze which is caused by skb->truesize which is used in kernel. Driver can work with actual mtu size and prepared skb buffer for it. This change also caused that dma_map/unmap operations take less time because of cache handling. xenet_change_mtu function close device. Free all preallocated buffers with old mtu size, enable dma engine, prepared skb buffer with new mtu size and open it again. Signed-off-by: Michal Simek <monstr@monstr.eu> | 02 June 2010, 17:24:20 UTC |
| 3113b3e | Michal Simek | 07 May 2010, 08:29:47 UTC | ll_temac: Use netdev_alloc_skb_ip_align instead of alloc_skb It is proposed change by Eric Dumazet <eric.dumazet@gmail.com> Signed-off-by: Steven J. Magnani <steve@digidescorp.com> Signed-off-by: Michal Simek <monstr@monstr.eu> | 02 June 2010, 17:20:11 UTC |
| 36e1e29 | John Linn | 24 May 2010, 20:33:06 UTC | Merge branch 'master-2.6.34' of ../../../linux_mb/devel/linux-2.6-xlnx | 24 May 2010, 20:33:06 UTC |
| 5fdfb97 | John Linn | 24 May 2010, 17:42:44 UTC | Merge branch 'master-2.6.34' of ../../../linux_ppc/linux-2.6 into master-2.6.34 Resolved Conflicts: arch/microblaze/Kconfig arch/microblaze/configs/mmu_defconfig arch/microblaze/include/asm/io.h arch/microblaze/include/asm/pci-bridge.h arch/microblaze/include/asm/pci.h arch/microblaze/include/asm/pgalloc.h arch/microblaze/include/asm/prom.h arch/microblaze/include/asm/tlbflush.h arch/microblaze/kernel/cpu/cache.c arch/microblaze/kernel/dma.c arch/microblaze/kernel/entry.S arch/microblaze/kernel/head.S arch/microblaze/mm/consistent.c arch/microblaze/mm/init.c arch/microblaze/pci/pci-common.c arch/microblaze/pci/pci_32.c arch/microblaze/pci/xilinx_pci.c drivers/input/keyboard/Makefile drivers/spi/xilinx_spi.c | 24 May 2010, 17:42:44 UTC |
| d5c6453 | John Linn | 19 May 2010, 20:51:22 UTC | Xilinx: ARM: SMP hacks for Palladium early SMP testing These changes create a kernel that boots on both CPUs. The code appears to be pretty brittle still as small changes can keep the kernel from booting all the way and it's not clear why. Since we don't have any control of the processor right now in Palladium the problem is hard to debug. This code has code that should be in a boot loader as the kernel entry point is holding CPU1 til CPU0 gets thru some initialization and then signals to let CPU1 go into the kernel also. A new kernel default configuration file was added to help with SMP testing (xilinx_palladium_smp_defconfig). I know it's a long name but it will go anyway one day anyway. This code does assume a special init code that is a hacked version of Rob Pelts. It's not cleaned up yet. It basically boots both CPUs to 0x8000 with some synchronization between them for the SCU filter initialization as that's where DDR gets valid. Both CPUs are going thru main. | 19 May 2010, 21:03:20 UTC |
| e40152e | Linus Torvalds | 16 May 2010, 21:17:36 UTC | Linus 2.6.34 | 16 May 2010, 21:17:36 UTC |
| b5dbc85 | Linus Torvalds | 16 May 2010, 18:11:53 UTC | Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6 * git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6: rtnetlink: make SR-IOV VF interface symmetric sctp: delete active ICMP proto unreachable timer when free transport tcp: fix MD5 (RFC2385) support | 16 May 2010, 18:11:53 UTC |
| d34e14f | Linus Torvalds | 16 May 2010, 18:11:31 UTC | Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus * 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: MIPS: Oprofile: Fix Loongson irq handler MIPS: N32: Use compat version for sys_ppoll. MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1 | 16 May 2010, 18:11:31 UTC |
| c02db8c | Chris Wright | 16 May 2010, 08:05:45 UTC | rtnetlink: make SR-IOV VF interface symmetric Now we have a set of nested attributes: IFLA_VFINFO_LIST (NESTED) IFLA_VF_INFO (NESTED) IFLA_VF_MAC IFLA_VF_VLAN IFLA_VF_TX_RATE This allows a single set to operate on multiple attributes if desired. Among other things, it means a dump can be replayed to set state. The current interface has yet to be released, so this seems like something to consider for 2.6.34. Signed-off-by: Chris Wright <chrisw@sous-sol.org> Signed-off-by: David S. Miller <davem@davemloft.net> | 16 May 2010, 08:05:45 UTC |
| 55fa0cf | Wei Yongjun | 09 May 2010, 16:56:07 UTC | sctp: delete active ICMP proto unreachable timer when free transport transport may be free before ICMP proto unreachable timer expire, so we should delete active ICMP proto unreachable timer when transport is going away. Signed-off-by: Wei Yongjun <yjwei@cn.fujitsu.com> Acked-by: Vlad Yasevich <vladislav.yasevich@hp.com> Signed-off-by: David S. Miller <davem@davemloft.net> | 16 May 2010, 07:46:22 UTC |
| 35790c0 | Eric Dumazet | 16 May 2010, 07:34:04 UTC | tcp: fix MD5 (RFC2385) support TCP MD5 support uses percpu data for temporary storage. It currently disables preemption so that same storage cannot be reclaimed by another thread on same cpu. We also have to make sure a softirq handler wont try to use also same context. Various bug reports demonstrated corruptions. Fix is to disable preemption and BH. Reported-by: Bhaskar Dutta <bhaskie@gmail.com> Signed-off-by: Eric Dumazet <eric.dumazet@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net> | 16 May 2010, 07:34:04 UTC |
| 4e73238 | Wu Zhangjin | 06 May 2010, 16:59:46 UTC | MIPS: Oprofile: Fix Loongson irq handler The interrupt enable bit for the performance counters is in the Control Register $24, not in the counter register. loongson2_perfcount_handler(), we need to use Reported-by: Xu Hengyang <hengyang@mail.ustc.edu.cn> Signed-off-by: Wu Zhangjin <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1198/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> --- | 15 May 2010, 20:59:54 UTC |
| 46afb82 | Chandrakala Chavva | 11 May 2010, 00:11:54 UTC | MIPS: N32: Use compat version for sys_ppoll. The sys_ppoll() takes struct 'struct timespec'. This is different for the N32 and N64 ABIs. Use the compat version to do the proper conversions. Signed-off-by: David Daney <ddaney@caviumnetworks.com> To: linux-mips@linux-mips.org Patchwork: http://patchwork.linux-mips.org/patch/1210/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> --- | 15 May 2010, 20:59:53 UTC |
| 95e8f63 | Shane McDonald | 07 May 2010, 05:26:57 UTC | MIPS FPU emulator: allow Cause bits of FCSR to be writeable by ctc1 In the FPU emulator code of the MIPS, the Cause bits of the FCSR register are not currently writeable by the ctc1 instruction. In odd corner cases, this can cause problems. For example, a case existed where a divide-by-zero exception was generated by the FPU, and the signal handler attempted to restore the FPU registers to their state before the exception occurred. In this particular setup, writing the old value to the FCSR register would cause another divide-by-zero exception to occur immediately. The solution is to change the ctc1 instruction emulator code to allow the Cause bits of the FCSR register to be writeable. This is the behaviour of the hardware that the code is emulating. This problem was found by Shane McDonald, but the credit for the fix goes to Kevin Kissell. In Kevin's words: I submit that the bug is indeed in that ctc_op: case of the emulator. The Cause bits (17:12) are supposed to be writable by that instruction, but the CTC1 emulation won't let them be updated by the instruction. I think that actually if you just completely removed lines 387-388 [...] things would work a good deal better. At least, it would be a more accurate emulation of the architecturally defined FPU. If I wanted to be really, really pedantic (which I sometimes do), I'd also protect the reserved bits that aren't necessarily writable. Signed-off-by: Shane McDonald <mcdonald.shane@gmail.com> To: anemo@mba.ocn.ne.jp To: kevink@paralogos.com To: sshtylyov@mvista.com Patchwork: http://patchwork.linux-mips.org/patch/1205/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> --- | 15 May 2010, 20:59:53 UTC |
| 18e41da | Linus Torvalds | 15 May 2010, 19:55:31 UTC | Merge git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-unstable * git://git.kernel.org/pub/scm/linux/kernel/git/mason/btrfs-unstable: Btrfs: check for read permission on src file in the clone ioctl | 15 May 2010, 19:55:31 UTC |
| 43aa7ac | kirjanov@gmail.com | 15 May 2010, 16:32:34 UTC | lib/btree: fix possible NULL pointer dereference mempool_alloc() can return null in atomic case. Signed-off-by: Denis Kirjanov <kirjanov@gmail.com> Cc: Joern Engel <joern@logfs.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> | 15 May 2010, 19:48:10 UTC |
| bdef2fe | Nicolas Ferre | 15 May 2010, 16:32:31 UTC | mmc: at91_mci: modify cache flush routines As we were using an internal dma flushing routine, this patch changes to the DMA API flush_kernel_dcache_page(). Driver is able to compile now. [akpm@linux-foundation.org: flush_kernel_dcache_page() comes before kunmap_atomic()] Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com> Cc: James Bottomley <James.Bottomley@HansenPartnership.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org> | 15 May 2010, 19:48:10 UTC |
| 5dc6416 | Dan Rosenberg | 15 May 2010, 15:27:37 UTC | Btrfs: check for read permission on src file in the clone ioctl The existing code would have allowed you to clone a file that was only open for writing Signed-off-by: Chris Mason <chris.mason@oracle.com> | 15 May 2010, 16:05:50 UTC |
| 3f8bf8f | Linus Torvalds | 15 May 2010, 16:03:15 UTC | Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6 * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/viro/vfs-2.6: JFS: Free sbi memory in error path fs/sysv: dereferencing ERR_PTR() Fix double-free in logfs Fix the regression created by "set S_DEAD on unlink()..." commit | 15 May 2010, 16:03:15 UTC |
| c28f3f8 | Linus Torvalds | 15 May 2010, 16:03:02 UTC | Merge branch 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'perf-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: perf record: Add a fallback to the reference relocation symbol | 15 May 2010, 16:03:02 UTC |
| 684bdc7 | Jan Blunck | 12 April 2010, 23:44:08 UTC | JFS: Free sbi memory in error path I spotted the missing kfree() while removing the BKL. [akpm@linux-foundation.org: avoid multiple returns so it doesn't happen again] Signed-off-by: Jan Blunck <jblunck@suse.de> Cc: Dave Kleikamp <shaggy@austin.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> | 15 May 2010, 11:16:34 UTC |
| 404e781 | Dan Carpenter | 21 April 2010, 10:30:32 UTC | fs/sysv: dereferencing ERR_PTR() I moved the dir_put_page() inside the if condition so we don't dereference "page", if it's an ERR_PTR(). Signed-off-by: Dan Carpenter <error27@gmail.com> Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> | 15 May 2010, 11:16:33 UTC |
| 2656244 | Al Viro | 29 April 2010, 00:57:02 UTC | Fix double-free in logfs iput() is needed *until* we'd done successful d_alloc_root() Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> | 15 May 2010, 11:16:33 UTC |
