| d70a652 | Michael Gill | 23 June 2016, 16:55:24 UTC | staging: apf: Fix crash in APF DMA associated with IP change The SG-DMA IP changed slightly, causing the APF DMA to occasionally fail to correctly write 64-bit addresses to IP registers. This change corrects that problem. Signed-off-by: Michael Gill <gill@xilinx.com> Tested-by: Christian Kohn <christian.kohn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 24 June 2016, 09:57:26 UTC |
| dfb97bc | Michael Gill | 08 June 2016, 22:15:34 UTC | staging: apf: Adding try-wait support for APF DMA This patch adds a non-blocking poll of the scatter-gather APF DMA done state. This is used to implement 'try-wait', which is a new feature introduced into user space runtimes for SDSoC. Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 09 June 2016, 05:45:17 UTC |
| 7ef509a | Michael Gill | 08 June 2016, 22:15:27 UTC | staging: apf: Enable malloc on MPSoC in APF DMA This patch enables use of 64-bit DMA IP, and removes the barrier blocking the use of malloc-allocated memory in SDSoC programs on MPSoC. Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 09 June 2016, 05:45:17 UTC |
| 211a753 | Soren Brinkmann | 07 June 2016, 20:17:43 UTC | zynqmp: pm: Don't issue SMC calls before driver is initialized Don't issue any SMC calls to the FW before the driver is properly initialized and discovered a valid FW. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 08 June 2016, 06:02:35 UTC |
| 4ed8ffc | Wendy Liang | 05 June 2016, 07:45:45 UTC | Revert "Documentation: r5_remoteproc: update reg example" This reverts commit 278aa45c1b441b3162cc745039a0f8a917a1edcf. As in arm64, the size cell is still "1". Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 06 June 2016, 06:44:09 UTC |
| aa67923 | Wendy Liang | 06 June 2016, 04:59:40 UTC | remoteproc: remove memset from rp_find_vq As the vring memory is already memset to 0 in rproc_alloc_vring() through dma_alloc_coherent(). It is duplicated to memset vring to 0 again. Signed-off-by: Wendy Liang <jliang@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 06 June 2016, 06:42:38 UTC |
| 589d1b6 | Preetesh Parekh | 03 June 2016, 02:21:46 UTC | drm: xilinx: crtc: Add crtc set config helper The goal is to be able to synchronize resolution changes between the drm device and emulated fbdev device if both devices are used by an application e.g. in Qt we use both graphics and video layer whereas the former is controlled by fbdev and the latter by drm. This patch propagates resolution changes from the drm device to fbdev. Before setting the new mode, a copy of the old mode is saved locally and restored upon last close. work in progres: If hot-plug events happen while the application is running, the mode pre-application start will be restored instead of the mode set by the last hot-plug event. For example if we switch monitors from 1080p to 4k while the application is running, last close will restore the fbconsole to 1080p on the 4k monitor. The framebuffer for the fbdev emulation is allocated when the driver is initialized, thus hotplug between monitors with different resolutions (ex, 2560x1440->1920x1080) wouldn’t work correctly as of now. Signed-off-by: Preetesh Parekh <preetesh.parekh@xilinx.com> Tested-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 03 June 2016, 13:03:22 UTC |
| ab52f93 | Michael Gill | 03 June 2016, 01:21:20 UTC | staging: apf: Fixed DMA-BUF used of buffers spanning partial pages The DRM infrastructure when using the xilinx driver has a potential to return a buffer mapped to a memory region spanning a partial page, such as in the case of a 1920x1080 resolution buffer. When this happens, the scatterlist returned from the DRM API describes a region rounded up to a whole page. This patch trims the returned scatterlist, thus making it usable by a DMA. Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Christian Kohn <christian.kohn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 03 June 2016, 13:02:51 UTC |
| 963f3be | Michael Gill | 03 June 2016, 01:21:19 UTC | staging: apf: Fix length for non-aligned(4K) DMA-BUF SG Iterate through DMA-BUF SG list and set length equal to buffer size. Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Christian Kohn <christian.kohn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 03 June 2016, 13:02:49 UTC |
| 9c24c44 | Kedareswara rao Appana | 01 June 2016, 12:42:17 UTC | irqchip: irq-xilinx-intc: Fix race condition in the irq flow handlers This commit bd0b9ac405e1 ("genirq: Remove irq argument from irq flow handlers") Modified the number of arguments of the irq flow handlers. With the current driver we are seeing a kernel crash because of the above commit. Crash log: Unable to handle kernel NULL pointer dereference at virtual address 0000002c pgd = c0004000 [0000002c] *pgd=00000000 Internal error: Oops - BUG: 17 [#1] PREEMPT SMP ARM Modules linked in: axi_timer CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.4.0-xilinx #5 Hardware name: Xilinx Zynq Platform task: c0923870 ti: c091e000 task.ti: c091e000 PC is at intc_handler+0x18/0x8c LR is at 0x1 pc : [<c01e91cc>] lr : [<00000001>] psr: 60010193 sp : c091fee0 ip : 00000002 fp : 00000001 r10: 00000000 r9 : 00000008 r8 : 00000001 r7 : ef002600 r6 : c091a464 r5 : 00000010 r4 : 00000000 r3 : 00000000 r2 : 00000000 r1 : ef003c40 r0 : 00000000 Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment none Control: 18c5387d Table: 2f16c04a DAC: 00000051 Process swapper/0 (pid: 0, stack limit = 0xc091e210) Stack: (0xc091fee0 to 0xc0920000) fee0: 00000000 00000000 c091a464 ef002600 00000001 c00576ec 00000000 c00579a8 ff00: f8f00100 c0920f7c c091ff30 c092ec00 f8f01100 c00093ac c0383918 60010013 ff20: ffffffff c091ff64 638ff226 c0013014 00000000 00000008 c091d000 ef7d7000 ff40: ef7d6618 00000001 7725eac9 00000008 638ff226 00000008 00000000 00000001 ff60: 00000008 c091ff80 c03838f4 c0383918 60010013 ffffffff 00000051 c03838e8 ff80: 3b993807 00000000 7725eac9 00000008 c091e000 ef7d6618 c091e000 c094d0e0 ffa0: c0919364 c091ffb8 c06aba30 00000000 00000000 c0050538 c0920400 c067ebdc ffc0: ffffffff ffffffff 00000000 c067e66c 00000000 c06aba30 00000000 c0954b94 ffe0: c0920480 c06aba2c c0924984 0000406a 413fc090 0000807c 00000000 00000000 [<c01e91cc>] (intc_handler) from [<c00576ec>] (generic_handle_irq+0x18/0x28) [<c00576ec>] (generic_handle_irq) from [<c00579a8>] (__handle_domain_irq+0x88/0xb0) [<c00579a8>] (__handle_domain_irq) from [<c00093ac>] (gic_handle_irq+0x50/0x90) [<c00093ac>] (gic_handle_irq) from [<c0013014>] (__irq_svc+0x54/0x90) Exception stack(0xc091ff30 to 0xc091ff78) ff20: 00000000 00000008 c091d000 ef7d7000 ff40: ef7d6618 00000001 7725eac9 00000008 638ff226 00000008 00000000 00000001 ff60: 00000008 c091ff80 c03838f4 c0383918 60010013 ffffffff [<c0013014>] (__irq_svc) from [<c0383918>] (cpuidle_enter_state+0xe8/0x1bc) [<c0383918>] (cpuidle_enter_state) from [<c0050538>] (cpu_startup_entry+0x19c/0x1ec) [<c0050538>] (cpu_startup_entry) from [<c067ebdc>] (start_kernel+0x328/0x388) Code: ebf9c52b e3500000 15904010 01a04000 (e595301c) ---[ end trace 1b82d42394b8ee22 ]--- Kernel panic - not syncing: Fatal exception in interrupt CPU1: stopping CPU: 1 PID: 0 Comm: swapper/1 Tainted: G D 4.4.0-xilinx #5 Hardware name: Xilinx Zynq Platform [<c00163b8>] (unwind_backtrace) from [<c0012620>] (show_stack+0x10/0x14) [<c0012620>] (show_stack) from [<c01c824c>] (dump_stack+0x80/0xcc) [<c01c824c>] (dump_stack) from [<c0014c2c>] (ipi_cpu_stop+0x3c/0x6c) [<c0014c2c>] (ipi_cpu_stop) from [<c0015344>] (handle_IPI+0x64/0x84) [<c0015344>] (handle_IPI) from [<c00093d0>] (gic_handle_irq+0x74/0x90) [<c00093d0>] (gic_handle_irq) from [<c0013014>] (__irq_svc+0x54/0x90) Exception stack(0xef06bf68 to 0xef06bfb0) bf60: 00000000 00000008 c091d000 ef7e3000 ef7e2618 00000001 bf80: 845530d3 00000008 668ca7c3 00000008 00000000 00000001 00000008 ef06bfb8 bfa0: c03838f4 c0383918 600d0013 ffffffff [<c0013014>] (__irq_svc) from [<c0383918>] (cpuidle_enter_state+0xe8/0x1bc) [<c0383918>] (cpuidle_enter_state) from [<c0050538>] (cpu_startup_entry+0x19c/0x1ec) [<c0050538>] (cpu_startup_entry) from [<0000948c>] (0x948c) ---[ end Kernel panic - not syncing: Fatal exception in interrupt This patch fixes this issue in the driver --> By updating the number of arguments in the flow handler to one. --> Use irq_desc_get_chip instead of irq_get_chip Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 01 June 2016, 13:09:33 UTC |
| 62348df | Michael Gill | 20 May 2016, 19:40:21 UTC | staging: apf: Fixed buffer over run related to page pinning The data structure used for storing pinned user space page structures was a constant size. Now it is adjustable to accommodate large transfers from malloc allocated buffers Signed-off-by: Michael Gill <gill@xilinx.com> Tested-by : Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 01 June 2016, 11:34:51 UTC |
| c5af5bd | Michael Gill | 20 May 2016, 19:40:05 UTC | staging: apf: Enable MPSoC SG-DMA and removed clock control This patch enables preliminary scatter-gather support for the apf DMA driver. This extends only to memory allocated by a call to sds_alloc, and dma_buf shared buffers. Zynq support is unchanged. Additionally, control over clocks has been removed due to clocks being correctly configured during petalinux boot. There is no impact of this on a user. Signed-off-by: Michael Gill <gill@xilinx.com> Tested-by : Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 01 June 2016, 11:34:39 UTC |
| ebe83ac | Michal Simek | 01 June 2016, 11:33:14 UTC | ARM: zynq: Enable RealTek phy for zynq RealTek phy is a common phy on some dc cards. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 01 June 2016, 11:33:57 UTC |
| 102e629 | Naga Sureshkumar Relli | 27 May 2016, 10:10:53 UTC | spi: xilinx: Update devicetree bindings for spi-xilinx Update bindings for spi-xilinx. as per spi-bus.txt rename num-ss-bits to num-cs. and add fifo-size and bits-per-word properties. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 31 May 2016, 16:54:42 UTC |
| 57c042c | Shubhrajyoti Datta | 09 March 2016, 08:47:20 UTC | spi: xilinx: Add devicetree binding for spi-xilinx Add a binding document for the spi/spi-xilinx Sync with mainline. Signed-off-by: Shubhrajyoti Datta <shubhraj@xilinx.com> Signed-off-by: Mark Brown <broonie@kernel.org> | 31 May 2016, 16:54:42 UTC |
| 30ffe6b | Naga Sureshkumar Relli | 27 May 2016, 10:10:52 UTC | spi: xilinx: Add QUAD support This patch adds QUAD mode support to axi spi controller. updated supported mode bits to SPI_TX_QUAD and SPI_RX_QUAD. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 31 May 2016, 16:54:42 UTC |
| b52e908 | Naga Sureshkumar Relli | 27 May 2016, 10:10:51 UTC | spi: xilinx: Remove bitbang and register with spi core This patch removes the bitbang layer registration. it directly register with spi core using spi_register_master and uses the call backs provided by spi_master struct. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 31 May 2016, 16:54:41 UTC |
| f1f2a61 | Michal Simek | 30 May 2016, 11:39:27 UTC | ARM64: zynqmp: Fix phy entry possition in defconfig Fix phy entry defconfig position. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 May 2016, 11:41:37 UTC |
| 8878ada | Michal Simek | 30 May 2016, 11:38:41 UTC | ARM64: zynqmp: Enable EFI by default By using toolchain from 2016.1 EFI can be enabled by default. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 May 2016, 11:41:37 UTC |
| 278aa45 | Wendy Liang | 26 May 2016, 18:23:42 UTC | Documentation: r5_remoteproc: update reg example Update the reg property example to follow the aarch64 platform device reg property format: * address-cells = <2>; * size-cells = <2>; Signed-off-by: Wendy Liang <jliang@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 27 May 2016, 08:34:52 UTC |
| 18403b0 | Wendy Liang | 26 May 2016, 18:23:41 UTC | remoteproc: ZynqMP R5: remove HVC/SMC functions Cleans up unused HVC/SMC implementation from ZynqMP R5 remoteproc. Signed-off-by: Wendy Liang <jliang@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 27 May 2016, 08:34:52 UTC |
| 20682ac | P L Sai Krishna | 26 May 2016, 13:54:18 UTC | mmc: sdhci-of-arasan: Add "SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12" quirk. Arasan controller supports AUTO CMD12, this patch adds "SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12" quirk to enable auto cmd12 feature. By using auto cmd12 we can also avoid following error message "Got data interrupt even though no data operation in progress" Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 27 May 2016, 08:34:51 UTC |
| cf7b313 | P L Sai Krishna | 26 May 2016, 13:54:17 UTC | mmc: Modified the SD standard speed to 19MHz. SD standard speed timing was met only at 19MHz and not 25 MHz, that's why changing driver to 19MHz. The reason for this is when a level shifter is used on the board, timing was met for standard speed only at 19MHz. since this level shifter is commonly required for high speed modes, the driver is modified to use standard speed of 19Mhz. This applies only for ZynqMPSoC. Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 27 May 2016, 08:34:51 UTC |
| f0e76bf | P L Sai Krishna | 26 May 2016, 13:54:16 UTC | mmc: sdhci-of-arasan: Merge mainline changes. This patch merge the mainline changes for sdhci-of-arasan. Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 27 May 2016, 08:34:50 UTC |
| ef638b1 | Michal Simek | 25 May 2016, 18:09:35 UTC | ARM64: zynqmp: Add gpio-keys for zcu102 There is gpio push button on MIO22. Add it to DTS to have full board description. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 May 2016, 18:44:17 UTC |
| 9d21870 | Michal Simek | 25 May 2016, 13:25:19 UTC | device-tree: Fix typo in phy binding doc Trivial fix. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 May 2016, 13:42:11 UTC |
| 54e468a | Michal Simek | 25 May 2016, 13:23:25 UTC | ARM64: zynqmp: Move serdes node to the right location Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 May 2016, 13:42:11 UTC |
| b99ee03 | Naga Sureshkumar Relli | 18 May 2016, 06:53:13 UTC | ARM64: zynqmp: Add ocm node in dtsi This patch adds ocm controller node in zynqmp.dtsi. needed for OCM edac support. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 May 2016, 09:41:13 UTC |
| e00f185 | Hyun Kwon | 18 May 2016, 18:54:35 UTC | drm: xilinx: dp: Use phy APIs Configure the phy through generic PHY APIs. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:37 UTC |
| d31ed1b | Hyun Kwon | 18 May 2016, 18:54:34 UTC | dma: xilinx: dpdma: Enable interrupts when enable channels The DPDMA can be reset at runtime, thus it's safer to enable / disable channel related interrupts when each channel is enabled. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:36 UTC |
| bc87c2f | Hyun Kwon | 17 May 2016, 11:19:10 UTC | ARM64: zynqmp: zcu102: Add phy phandles to DisplayPort Add phy phandles to the DisplayPort DT node. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:36 UTC |
| c812a8f | Hyun Kwon | 17 May 2016, 11:19:09 UTC | dt: bindings: drm: dp: Add PHY properties The ZynqMP can have phy phandles in the DP node to work with ZynqMP PHY driver. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:35 UTC |
| 6e6bf62 | Anurag Kumar Vulisha | 17 May 2016, 11:19:08 UTC | Revert "ARM64: zynqmp: Add serdes address space dp driver" This reverts commit a11218ab4245b17e331472a8293d399f7ecb8d93 Since we are using serdes driver , no need of mapping serdes register space into DP driver. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:35 UTC |
| e144f4e | Anurag Kumar Vulisha | 17 May 2016, 11:19:07 UTC | Revert "drm: xilinx: dp: Program SERDES register when training" This reverts commit a06b1a4444e6304039c32d08562554b260f5904a. Since we are using serdes driver, so no need to program serdes for DP link training. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:34 UTC |
| 86540e8 | Anurag Kumar Vulisha | 17 May 2016, 11:19:06 UTC | devicetree: usb: Add phys phandle property in usb node This patch adds phys phandle property in usb node for using zynqmp phy driver. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:34 UTC |
| 049ffc8 | Anurag Kumar Vulisha | 17 May 2016, 11:19:05 UTC | devicetree: ata: Add phys phandle property in sata node This patch adds phys phandle property in sata node for using zynqmp phy driver. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:33 UTC |
| 9928a9b | Anurag Kumar Vulisha | 17 May 2016, 11:19:04 UTC | devicetree: phy: Include phy.h in dts files This patch adds phy.h include file from dt-bindings. This is used for adding phandles to phy driver by high speed pheripherals like SATA, USB, Display Port, PCIe and SGMII in their device tree nodes. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:33 UTC |
| c9e103f | Anurag Kumar Vulisha | 17 May 2016, 11:19:03 UTC | devicetree: phy: Add ZynqMP GT core support to zcu102 This patch adds Zynqmp Phy spport to zcu102 board Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:33 UTC |
| 9e38c0d | Anurag Kumar Vulisha | 17 May 2016, 11:19:02 UTC | devicetree: phy: Add Zynqmp Phy core support to DC1 board This patch adds Zynqmp Phy support to DC1 boards Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:32 UTC |
| 018c87c | Anurag Kumar Vulisha | 17 May 2016, 11:19:01 UTC | devicetree: phy: add device tree properties for ZynqMP GT core This patch adds the ZynqMP GT core device-tree properties for zynqmp.dtsi file. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:32 UTC |
| e4d9cc4 | Anurag Kumar Vulisha | 17 May 2016, 11:19:00 UTC | ARM64: zynqmp: Enable Zynqmp Phy driver by default This patch enables the zynqmp serdes driver used by high speed pheripherals like SATA, USB, DP, PCIe and SGMII Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:31 UTC |
| 3e52d4a | Hyun Kwon | 17 May 2016, 11:18:59 UTC | phy: zynqmp: Add DisplayPort custom functions to serdes driver The DisplayPort requires programming of preemphasis / voltage swing value at runtime. These functions will be called from DisplayPort driver when required. This patch adds the same. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:31 UTC |
| 91fb3a2 | Anurag Kumar Vulisha | 17 May 2016, 11:18:58 UTC | phy: zynqmp: Add phy driver for xilinx zynqmp phy core ZynqMP SoC has a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:30 UTC |
| 4a3c71e | Anurag Kumar Vulisha | 17 May 2016, 11:18:57 UTC | phy: Add Display port and SGMII type PHYs This patch adds two new macros for specifying Display Port and SGMII PHYs. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:30 UTC |
| 6e1c242 | Anurag Kumar Vulisha | 17 May 2016, 11:18:56 UTC | phy: zynqmp: Add dt bindings for ZynqMP PHY This patch adds the document describing dt bindings for ZynqMP PHY. ZynqMP SOC has a High Speed Processing System Gigabit Transceiver which provides PHY capabilties to USB, SATA, PCIE, Display Port and Ehernet SGMII controllers. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Tested-by: Hyun Kwon <hyunk@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 May 2016, 11:53:30 UTC |
| 63bcc8b | Iban Rodriguez | 13 May 2016, 10:11:46 UTC | gpio: xilinx: Add support to set multiple GPIO at once Add function to set multiple GPIO of the same chip at the same time and register it. Signed-off-by: Iban Rodriguez <irodriguez@cemitec.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 17 May 2016, 05:22:57 UTC |
| 96ce8fc | Alexander Graf | 12 May 2016, 11:44:01 UTC | ARM64: zynqmp: Align gic ranges for 64k in device tree The GIC ranges in the zynqmp device tree are only 4kb aligned. Since commit 12e14066f we automatically deal with aliases GIC regions though, so we can map them transparently into guests even on 64kb page size systems. This patch makes use of that features and sets GICC and GICV to 64kb aligned and sized regions. Signed-off-by: Alexander Graf <agraf@suse.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 16 May 2016, 07:13:31 UTC |
| 426ad45 | Topi Kuutela | 11 May 2016, 11:53:41 UTC | gpio: xilinx: Fix irq-handler prototype Updated irq-handler to correspond to the prototype change of commit bd0b9ac405e1 ("genirq: Remove irq argument from irq flow handlers"). Signed-off-by: Topi Kuutela <topi.kuutela@murata.com> Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 16 May 2016, 06:34:41 UTC |
| 06416af | Topi Kuutela | 11 May 2016, 09:55:51 UTC | i2c: cadence: Fix power management order of operations E.g. pm_runtime_set_active must be called while the power management system is disabled. Fixes extra hanging clk_enable. Signed-off-by: Topi Kuutela <topi.kuutela@murata.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 16 May 2016, 06:34:41 UTC |
| eb7ad67 | Punnaiah Choudary Kalluri | 10 May 2016, 18:46:19 UTC | net: macb: Fix kernel crash when MACB_EXT_BD is enabled When MACB_EXT_BD config option is enabled, while sending TCP data, observing Kernel crash due to NULL pointer dereference. Added fix to ensure skb is a valid pointer before dereferencing it for checking the time stamp option. Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Acked-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 May 2016, 06:05:40 UTC |
| c47c954 | Michal Simek | 06 May 2016, 05:42:14 UTC | Revert "drm: xilinx: crtc: Add crtc set config helper" This reverts commit dd7c1f0b5c23bcac5046d77bd5e0631e657003a4. This patch is fixing problem with Qt and X11 when Mali driver is enabled. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 10 May 2016, 14:41:04 UTC |
| 28220d4 | Naga Sureshkumar Relli | 27 April 2016, 04:17:37 UTC | edac: zynqmp: Add EDAC support for ZynqMP OCM Controller This patch adds EDAC support for ZynqMP OCM Controller, this driver reports CE and UE errors based on interrupt, and also creates ue/ce sysfs entires for error injection. Also updated Kconfig and Makefile. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 03 May 2016, 06:40:34 UTC |
| ac5efa9 | Naga Sureshkumar Relli | 27 April 2016, 04:17:38 UTC | edac: zynqmp: Add device tree bindings for ZynqMP OCM Controller This patch adds device tree bindings for ZynqMP OCM Controller for EDAC. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 03 May 2016, 06:40:23 UTC |
| 7565c15 | Michal Simek | 06 April 2016, 08:43:23 UTC | ARM64: zynqmp: List all SMMU ids Add SMMU description for all tested IPs. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 03 May 2016, 06:35:55 UTC |
| 6aae55c | Michal Simek | 20 April 2016, 11:12:25 UTC | ARM64: zynqmp: Enable gpio-led as heartbeat on zcu102 Show user that Linux is alive on the board. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 03 May 2016, 06:35:55 UTC |
| 5b293e0 | Filip Drazic | 26 April 2016, 14:19:59 UTC | ARM64: zynqmp: Added supported PM reset IDs and actions In pm_defs.h added reset lines controlled with PM reset APIs and flags stating how to configure reset. Updated reset PM API definitions accordingly. Signed-off-by: Filip Drazic <filip.drazic@aggios.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 03 May 2016, 06:35:55 UTC |
| 00526bf | Kedareswara rao Appana | 29 April 2016, 10:04:22 UTC | net: ethernet: xilinx: Fix race condition for 10G MAC In the driver napi is enabled after interrupts are being registered. This may casue issue if there is already data in the mac rx fifo. If there is already data in the mac rx fifo in the current driver flow it will trigger RX ISR there we are disabling RX interrupts again it will get enabled after processing the packets upto quota in the napi poll. But with the current driver flow napi will never be called resulting no more rx packets being processed(As napi is enabled at the end of the open function). This patch fixes this issue. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Acked-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 03 May 2016, 06:35:12 UTC |
| 049400e | Kedareswara rao Appana | 29 April 2016, 10:04:21 UTC | net: ethernet: fix race condition for eth_irq eth_irq is valid only for 1G Ethernet case. For 10G MAC this interrupt won't be available. Fix if condition checks around eth_irq for the same. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Acked-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 03 May 2016, 06:35:11 UTC |
| eb6a0d2 | Naga Sureshkumar Relli | 20 April 2016, 05:05:20 UTC | edac: Enable CE and UE interrupts for ZynqMP DDRC This patch enables Corrected and Uncorrected Error interrupts for ZynqMP DDRC controller Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Reviewed-by: Punnaiah Choudary Kalluri<punnaia@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2016, 11:03:03 UTC |
| a455c5c | Michal Simek | 22 April 2016, 08:42:15 UTC | ARM64: zynqmp: Enable fhandle It is required by new systemd used on Linaro rootfs used for bring up. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2016, 10:38:22 UTC |
| 2009c4d | Anurag Kumar Vulisha | 20 April 2016, 15:47:35 UTC | rtc: zynqmp: Update seconds time programming logic We program RTC time using SET_TIME_WRITE register and read the RTC current time using CURRENT_TIME register. When we set the time by writing into SET_TIME_WRITE Register and immediately try to read the rtc time from CURRENT_TIME register, the previous old value is returned instead of the new loaded time. This is because RTC takes nearly 1 sec to update the new loaded value into the CURRENT_TIME register. This behaviour is expected in our RTC IP. This patch updates the driver to read the current time from SET_TIME_WRITE register instead of CURRENT_TIME when rtc time is requested within an 1sec period after setting the RTC time. Doing so will ensure the correct time is given to the user. Since there is a delay of 1sec in updating the CURRENT_TIME we are loading set time +1sec while programming the SET_TIME_WRITE register, doing this will give correct time without any delay when read from CURRENT_TIME. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> | 26 April 2016, 10:38:22 UTC |
| cbe1ff7 | Anurag Kumar Vulisha | 12 April 2016, 12:15:45 UTC | rtc: zynqmp: Write Calibration value before setting time It is suggested to program CALIB_WRITE register with the calibration value before updating the SET_TIME_WRITE register, doing so will clear the Tick Counter and force the next second to be signaled exactly in 1 second. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> | 26 April 2016, 10:38:21 UTC |
| ca5545a | Michal Simek | 07 April 2016, 13:11:21 UTC | ARM64: zynqmp: Use 32bit size cell format for amba busses But use 64bit size cells for memory nodes to be able to address more then 4GB memories in single block. It is revert of the patch "ARM64: zynqmp: Use 64bit size cell format" (sha1: 23b85c15be476948158c2c5f3af7945000fc92f9) which was rejected by Linux reviewers. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2016, 10:38:21 UTC |
| b564f31 | Michal Simek | 07 April 2016, 09:54:25 UTC | ARM: zynq: Fix usb phy node Compatible string should be the first property in node. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2016, 10:38:20 UTC |
| 8d1a604 | Michal Simek | 07 April 2016, 09:52:56 UTC | ARM: zynq: Enable qspi for Zybo Sync with U-Boot dts. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2016, 10:38:20 UTC |
| 3c0e5e0 | Michal Simek | 07 April 2016, 09:26:06 UTC | ARM: zynq: Sort DTS for various boards Use the same alphabelical order everywhere. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2016, 10:38:20 UTC |
| df357d0 | Michal Simek | 07 April 2016, 09:28:12 UTC | ARM: zynq: Use C pre-processor for includes in dts Change the dtsi include code to use the C pre-processor #include instead of the device tree /include/. This brings all ZynqMP device trees inline with each other. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2016, 10:38:19 UTC |
| e3a2cd8 | Michal Simek | 07 April 2016, 09:34:44 UTC | ARM: zynq: Use spi0 alias for qspi if it is present U-Boot Zynq variables expects to have qspi for saving variables as qspi0. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2016, 10:38:19 UTC |
| f106869 | Michal Simek | 07 April 2016, 09:23:34 UTC | ARM: zynq: Add mmc alias for zc702/zc706/zed/zybo Add missing mmc alias. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2016, 10:38:18 UTC |
| 34b4621 | Michal Simek | 07 April 2016, 09:22:21 UTC | ARM: zynq: Move gem node to be in proper location Keep alphabetical order in dts. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2016, 10:38:18 UTC |
| a800f3f | Michal Simek | 13 April 2016, 12:30:14 UTC | ARM64: zynqmp: Enable cadence watchdog driver It is available on ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2016, 10:38:18 UTC |
| dd7c1f0 | Preetesh Parekh | 25 April 2016, 19:02:45 UTC | drm: xilinx: crtc: Add crtc set config helper The goal is to be able to synchronize resolution changes between the drm device and emulated fbdev device if both devices are used by an application e.g. in Qt we use both graphics and video layer whereas the former is controlled by fbdev and the latter by drm. This patch propagates resolution changes from the drm device to fbdev. Before setting the new mode, a copy of the old mode is saved locally and restored upon last close. work in progres: If hot-plug events happen while the application is running, the mode pre-application start will be restored instead of the mode set by the last hot-plug event. For example if we switch monitors from 1080p to 4k while the application is running, last close will restore the fbconsole to 1080p on the 4k monitor. Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2016, 10:38:17 UTC |
| 9c1d910 | Hyun Kwon | 12 April 2016, 06:18:08 UTC | drm: xilinx: dp: Soft-reset after link training Soft-reset after link training and before enabling mainstream. This fixes the screen out-of-sync issue. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Tested-by: Christian Kohn <christian.kohn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 12 April 2016, 17:40:18 UTC |
| 72f82c5 | Michael Gill | 12 April 2016, 11:32:44 UTC | staging: apf: Added support for optional stock DMA driver Previously we exclusively used our own driver internal to apf for the DMA. This patch adds the option to instead use the normal Xilinx DMA driver. This isn't enabled by default. In addition to the new driver support, this patch introduces the ability for the user program to poll for the driver configuration, thus allowing the user program to use the correct DMA specific code. Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 12 April 2016, 15:53:39 UTC |
| b2092c1 | Chris Kohn | 08 April 2016, 00:48:51 UTC | media: adv7604: automatic "default-input" selection Add logic such that the "default-input" property becomes unnecessary for chips that only have one suitable input (ADV7611 by design, and ADV7612 due to commit 7111cddd "[media] media: adv7604: reduce support to first (digital) input"). Additionally, Ian's documentation in commit bf9c8227 ("[media] media: adv7604: ability to read default input port from DT") states that the "default-input" property should reside directly in the node for adv7612. Hence, also adjust the parsing to make the implementation consistent with this. Signed-off-by: William Towle <william.towle@codethink.co.uk> Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com> Requested-by: Chris Kohn <ckohn@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 12 April 2016, 10:34:48 UTC |
| 79af64c | Naga Sureshkumar Relli | 12 April 2016, 06:16:11 UTC | ARM64: zynqmp: Enable can1 for ep108 This patch enables can1 for ep108. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Reviewed-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 12 April 2016, 08:21:57 UTC |
| 322334a | Michael Gill | 12 April 2016, 05:48:10 UTC | staging: apf: Introductory MPSoC support Code has been moved to compile under 64-bit and 32-bit. MPSoC cache flushing now supported. Additionally, ioctl arguments have been moved to a data-width stable form, and correct data widths have been used throughout. This is the first MPSoC supporting patch Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 12 April 2016, 08:21:57 UTC |
| 3cb7229 | Michael Gill | 12 April 2016, 04:24:03 UTC | staging: apf: Fixed alignment of ioctl args Some changes to the user-space code resulted in a shift in the alignment of several arguments in structures that are used to communicate to the apf kernel driver via ioctl. This mirrors those changes in the kernel code. Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 12 April 2016, 05:20:00 UTC |
| bd78410 | VNSL Durga | 11 April 2016, 12:13:47 UTC | ARM64: zynqmp: Added clocks to DT for ep108 Added clks for ep108 platform. Signed-off-by: VNSL Durga <vnsldurg@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 April 2016, 13:32:48 UTC |
| f9dd59d | Michael Gill | 08 April 2016, 21:13:29 UTC | staging: apf: Modifications to match user-space xlnk lib changes Modified apf driver to conform to changes made in xlnk lib user-space code. Primarily this involves changes in internal DMA naming conventions and layout of structures used in ioctl calls. Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 April 2016, 06:31:56 UTC |
| 72690e1 | Michael Gill | 08 April 2016, 21:13:22 UTC | staging: apf: Made allocated buffers properly configure TLB. dma_alloc_coherent inherently assumes certain TLB settings, that we were then manually violating. Instead, user-space accessed DMA buffers are allocated using kmalloc, which we can make use of more flexibly. Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 April 2016, 06:31:55 UTC |
| 3affa58 | Michael Gill | 08 April 2016, 21:13:13 UTC | staging: apf: Fixed an error involving invalidation If a CPU wrote data to the cache, instructed a DMA to write to a sub-region an incomplete cache line, then read the line back, an incorrect data would be read. This stemmed from how the CPU invalidated the D-Cache after the DMA finished writing. The CPU would invalidate the entire block, assuming the DMA has written the entire block, thus losing the data that the CPU wrote that the DMA did not over-write. This is resolved by manually flushing the value down, and invalidating before the DMA write is issued, instead of invalidating after. Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 April 2016, 06:31:55 UTC |
| b861e53 | Michael Gill | 08 April 2016, 21:13:06 UTC | staging: apf: Fixes to error reporting There were several instances in which apf code could fail silently. This patch adds descriptive messages to the kernel debug log instead of just returning an error code. This is done to aid future debugging. Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 April 2016, 06:31:55 UTC |
| 9b663ba | Michael Gill | 08 April 2016, 21:11:52 UTC | staging: apf: Making regular use of constant for DMA structure sizes Originally a constant was defined to specify sizes of structures that track DMA state. This constant was not used, and instead a literal integer was used when interacting with these structures as a bound. This patch makes proper use of the defined constant, and abandons the literal. Signed-off-by: Michael Gill <gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 April 2016, 06:31:54 UTC |
| 18636b6 | P L Sai Krishna | 08 April 2016, 08:01:20 UTC | ARM64: zynqmp: Added is-dual property to QSPI node on zcu102 This patch adds is-dual property to QSPI node to configure QSPI for DUAL PARALLEL. Signed-off-by: P L Sai Krishna <lakshmis@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 08 April 2016, 10:58:03 UTC |
| 7a003fc | Michal Simek | 08 April 2016, 06:40:11 UTC | devicetree: udc-xilinx: Fix coding style in binding doc Fix indentation in example. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 08 April 2016, 06:47:24 UTC |
| 3d65b7b | Punnaiah Choudary Kalluri | 07 April 2016, 19:24:00 UTC | ARM: zynq: defconfig: Enable ULPI PHYs for Zynq Enabled the ULPI PHY for Zynq USB controller. Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 08 April 2016, 06:47:24 UTC |
| 3a20c69 | Manjukumar Matha | 06 April 2016, 18:43:49 UTC | ARM64: zynqmp: Enable EVDEV for Qt mouse/kb plugin EVDEV needs to be enabled for mouse/kb to work in QT Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 07 April 2016, 06:12:53 UTC |
| 109a7fc | Naga Sureshkumar Relli | 05 April 2016, 12:04:55 UTC | ARM64: zynqmp: Change usb node label representation This patch changes usb node label represenation. Our DTG is not able to recognize that usb node because the usb node label doesn't have ip address as like other ip nodes. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 05 April 2016, 12:52:07 UTC |
| 2696234 | Michal Simek | 05 April 2016, 10:01:16 UTC | ARM64: zynqmp: Fix usb nodes for ep108, dc1 and dc2 Fix DT binding for usb nodes. Setup correct aliases and enable dwc3 nodes. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 05 April 2016, 10:01:16 UTC |
| 7ce0094 | Kedareswara rao Appana | 04 April 2016, 07:04:09 UTC | Documentation: DT: Add binding documentation for axi emaclite Add device-tree binding documentation for the axi emaclite driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 04 April 2016, 12:29:03 UTC |
| 50df695 | Andrei-Liviu Simion | 01 April 2016, 22:13:32 UTC | drm: xilinx: dp: IRQ_HPD requires link status change check. Check if the link status has changed on an IRQ_HPD in order to determine if link training is required. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 04 April 2016, 06:42:03 UTC |
| 16d7629 | Andrei-Liviu Simion | 01 April 2016, 22:13:31 UTC | drm: xilinx: dp: Maximum pre-emphasis of 2 for ZynqMP. DisplayPort on ZynqMP has a maximum pre-emphasis level of 2. DisplayPort in soft IP has a maximum level of 3. Signed-off-by: Andrei-Liviu Simion <andrei.simion@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 04 April 2016, 06:42:02 UTC |
| a06b1a4 | Hyun Kwon | 01 April 2016, 22:13:30 UTC | drm: xilinx: dp: Program SERDES register when training SERDES registers should be programmed to predefined values during link training due to the hardware issue. This patch maps the SERDES registers directly, but the SERDES is shared between multiple devices. This patch will be reverted once the SERDES driver, phy-zynqmp is in place. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 04 April 2016, 06:42:00 UTC |
| 71af84f | Michal Simek | 23 February 2016, 08:30:15 UTC | ARM64: zynqmp: Add missing mmc aliases Add missing mmc aliases. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 01 April 2016, 13:35:33 UTC |
| 789ed70 | Siva Durga Prasad Paladugu | 05 November 2015, 12:37:26 UTC | ARM64: zynqmp: DC5: Add support for XM019 DC5 Add initial support for zc1751 xm019 dc5 support. It has GEM1 and SD0 enabled. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 01 April 2016, 13:35:30 UTC |
| ac9b035 | Naga Sureshkumar Relli | 01 April 2016, 09:47:40 UTC | edac: synopsys: Update ecc error message info This patch updates the ecc error message info for zynqmp ddrc. added Block number and Bankgroup in the message info. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 01 April 2016, 11:00:24 UTC |
| 8fa4484 | Naga Sureshkumar Relli | 01 April 2016, 09:47:39 UTC | edac: synopsys: Fix wrong ecc error log info Read ecc log info like bankgroup number,bank and blocknumber for CE and UE from CEADDR1 and UEADDR1 registers respectively. in previous case we are updating wrong log info. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 01 April 2016, 11:00:24 UTC |
| d6fa76d | Naga Sureshkumar Relli | 01 April 2016, 09:47:38 UTC | edac: synopsys: Fix incorrect defines and masks This patch fixes incorrect DDR control width defines and also ECC_CEADDR1_BLKNR_MASK value. Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 01 April 2016, 11:00:23 UTC |
| 71fe284 | Naga Sureshkumar Relli | 01 April 2016, 09:47:37 UTC | edac: synopsys: Add ecc error injection support The ZynqMP DDRC controller has data poisoning support to inject CE or UE errors. this patch adds this support using sysfs attributes. created the following sysfs entries to support this. -> /sys/devices/system/edac/mc/mc0/inject_data_poison -> /sys/devices/system/edac/mc/mc0/inject_data_error Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 01 April 2016, 11:00:16 UTC |
