| f1b1e07 | Manish Narani | 26 September 2017, 12:43:24 UTC | zynqmp: devicetree: Add no-1-8-v property to sdhci1 node This patch adds no-1-8-v property to sdhci1 node such that SD operates at 50MHz by default. To operate at UHS mode, this property can be removed from the sdhci1 node. Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 September 2017, 13:00:04 UTC |
| f193a37 | Rohit Athavale | 28 July 2017, 20:50:23 UTC | misc: xilinx-sdfec: make irq support an optional DT parameter This commit adds support to make Interrupt line information an optional parameter to support designs that do not use interrupts. Signed-off-by: Rohit Athavale <rathaval@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 13:32:20 UTC |
| 38e29cb | Rohit Athavale | 11 July 2017, 20:36:31 UTC | misc: xilinx-sdfec: initial driver support for xilinx sdfec This commit adds a char driver for SDFEC (Soft Decision FEC) IP. The Forward Error Correction(FEC) Engine is a Hard IP block which provides high throughput LDPC and Turbo Code implementations. Some of the driver design decisions were based on the following hardware behaviour: - In-band reset register was not present. External reset being provisioned depends on system designer. Driver needs to be notified of a reset by ioctl. - Codes cannot be updated on the fly and codes can be large. Codes are marshalled via ioctl to setup the device. - Interrupts indicate a failure of the SDFEC instance Signed-off-by: Rohit Athavale <rohit.athavale@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 13:32:13 UTC |
| 3917ea3 | Rohit Athavale | 11 July 2017, 20:36:30 UTC | documentation: device-tree: add bindings for xilinx sdfec driver This patch adds device tree bindings for the Xilinx SDFEC (16nm) driver. Signed-off-by: Rohit Athavale <rohit.athavale@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 13:32:10 UTC |
| ca1d7a1 | Nava kishore Manne | 19 September 2017, 09:10:55 UTC | arm64: zynqmp: Add support for ZynqMP RSA H/W accelerator This patch adds support for ZynqMP RSA H/W accelerator. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 06:50:02 UTC |
| f0cad69 | Nava kishore Manne | 19 September 2017, 09:10:54 UTC | crypto: zynqmp-rsa: Adopted RSA support for ZynqMP SoC This patch adds RSA (Encryption/Decryption) support for ZynqMP SoC. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 06:50:01 UTC |
| 8896e68 | Nava kishore Manne | 19 September 2017, 09:10:53 UTC | arm: dt: crypto: Added binding docs for Xilinx ZynqMP RSA H/W accelerator New bindings document for ZynqMP RSA H/W accelerator. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 06:50:01 UTC |
| b0e87ac | Nava kishore Manne | 19 September 2017, 09:10:52 UTC | arm64: zynqmp: Add support for zynqmp SHA3 H/W accelerator This patch Adds support for zynqmp SHA3 H/W accelerator. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 06:50:00 UTC |
| 6aa92ef | Nava kishore Manne | 19 September 2017, 09:10:51 UTC | crypto: zynqmp-sha: Adopted SHA3 support for ZynqMP Soc This patch adds SHA3 support for ZynqMP Soc. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 06:50:00 UTC |
| f050945 | Nava kishore Manne | 19 September 2017, 09:10:50 UTC | arm: dt: crypto: Added binding docs for Xilinx ZynqMP SHA3 H/W accelerator New bindings document for ZynqMP SHA3 H/W accelerator. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 06:49:59 UTC |
| 1d08a19 | Nava kishore Manne | 19 September 2017, 09:10:49 UTC | soc: zynqmp: Added pm api functions for RSA, SHA and AES This patch adds PM APIs to provided access to xilsecure library to calculate SHA3 hash on the data or to encrypt or decrypt the data using AES hardware engine and to encrypt or decrypt the data by using RSA public or private keys respectively. Signed-off-by: Durga Challa <vnsldurg@xilinx.com> Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 06:49:59 UTC |
| e1a214d | Harini Katakam | 19 September 2017, 09:15:50 UTC | net: macb: Misc cleanup This patch does the following cleanup to keep master in sync with rebase branch: - Correct comment style in one place - Correct coding style when using case in one place - Remove repeated code for setting DMA mask in the probe Signed-off-by: Harini Katakam <harinik@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 06:49:58 UTC |
| a7fbcf3 | Nava kishore Manne | 18 September 2017, 14:14:54 UTC | Revert "fpga manager: Adopted Authenticated BitStream loading support for Xilinx" This reverts commit ed5a1413206f479a2ec68205539af4e299ce8ee7. The FW (xilfpga) is using single pair of keys to authenticate the Image. According to the xilinx flow we need to use a pair of keys to provide the proper authentication support. currently the FW don't have this support. So this patch remove the Authenticated BitStream loading support. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 06:49:58 UTC |
| d14677a | Nava kishore Manne | 18 September 2017, 14:14:53 UTC | Revert "fpga manager: Adopted Device-Key Encrypted BitStream loading support for Xilinx zynqmp." This reverts commit 18df7049e07c67a04b14a4833d628fc82f49921e. This patch reverts the Deivce-key Encrypted BitStream loading support due to the security issues. Signed-off-by: Nava kishore Manne <navam@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 06:49:57 UTC |
| e24b9f2 | Michal Simek | 09 August 2017, 14:26:07 UTC | arm64: zynqmp: Add support for zc1275 revA Add DT file for zc1275 revA. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 20 September 2017, 06:49:57 UTC |
| 720dbab | Michal Simek | 30 June 2017, 06:39:35 UTC | arm64: zynqmp: Add support for Xilinx zc1254 board This patch adds support for Xilinx zc1254 board. Only QSPI(single) and uarts are wired on this board. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 September 2017, 08:57:16 UTC |
| f9658a4 | Michal Simek | 15 September 2017, 08:37:08 UTC | Revert "mmc: arasan: Add ADMA broken quirk based on DT parameter" This reverts commit 0e4e4071493171bbac37bf60709022f49171c813. It should be the part of: "zynq: devicetree: Remove 'broken-adma2' property" (sha1: fec1fe44076b1b2f8b7d6b2669697ea16b33a215) Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 September 2017, 08:45:28 UTC |
| 178bf52 | Michal Simek | 15 September 2017, 08:35:15 UTC | Revert "Documentation: mmc: Add broken-adma2 property" This reverts commit 358257734eea7ae4b16d91a5e91e940181448fd9. It should be the part of: "zynq: devicetree: Remove 'broken-adma2' property" (sha1: fec1fe44076b1b2f8b7d6b2669697ea16b33a215) Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 September 2017, 08:45:28 UTC |
| 203815f | Michal Simek | 15 September 2017, 06:54:32 UTC | Revert "ASoC: Add SPDIF DAI format" This reverts commit 80336ab140a467c469effb50d5467e1c45f28824. It should be the part of commit: "drm: i2c: adv7511: Remove non-mainline adv7511 driver" (sha1: c650bd1e08e6e42073ca7e2f68dfd9cb90e55366) Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 September 2017, 06:55:42 UTC |
| 338e502 | Michal Simek | 11 September 2017, 11:06:55 UTC | dma: Revert empty line Kconfig fix This change is done by my editor and it is not done in mainline that's why I am reverting it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 September 2017, 06:40:45 UTC |
| 79f1f46 | Michal Simek | 11 September 2017, 12:36:58 UTC | i2c: media: ad9389b: Use mainline version This file was changed in past because of TRD but it wasn't tested over time that's why several merges between probably breaks it. Changes which were done are already integreated in this kernel that's why this syncup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 September 2017, 06:32:19 UTC |
| a4ca80e | Michal Simek | 13 September 2017, 08:38:51 UTC | uapi: mtd: Remove unused mtd_locking_state enum These enum values are not used anywhere that's why remove them. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 September 2017, 06:32:05 UTC |
| 322e279 | Michal Simek | 13 September 2017, 11:27:26 UTC | dt-binding: Remove old zynq_edac binding This file was replaced by Documentation/devicetree/bindings/memory-controllers/synopsys.txt Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 September 2017, 06:31:51 UTC |
| dec4639 | Michal Simek | 13 September 2017, 13:20:17 UTC | spi: Fix kernel doc format in spi.h Document dummy variable which fix this kernel-doc issue. include/linux/spi/spi.h:778: warning: No description found for parameter 'dummy' Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 September 2017, 06:30:41 UTC |
| d9b52f2 | Michal Simek | 13 September 2017, 14:32:53 UTC | dt-binding: Remove MB remoteproc binding Driver was already removed by: "remoteproc: Remove unused mb remoteproc" (sha1: 3bcabd8e8726fc099ce86ad9e60c1c18c30f351b) Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 September 2017, 06:27:39 UTC |
| 2941fd3 | Michal Simek | 14 September 2017, 11:09:27 UTC | dt-bindings: zynq-gpio: Remove duplicated property in example Example contains the same properties. Remove one. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 September 2017, 06:27:27 UTC |
| 044fe38 | Wendy Liang | 14 September 2017, 18:22:03 UTC | remoteproc: elf loader: revert obsolete change This patch is to revert the change to get the loaded resource table which is no longer required. The change to remove is part of commit 106a1dc8416d ("Merge tag 'v3.10' into master-next") Signed-off-by: Wendy Liang <jliang@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 September 2017, 06:26:26 UTC |
| 7eb5f81 | Fahad Kunnathadi | 14 September 2017, 06:03:17 UTC | net: phy: Fix mask value write on gmii2rgmii converter speed register To clear Speed Selection in MDIO control register(0x10), ie, clear bits 6 and 13 to zero while keeping other bits same. Before AND operation,The Mask value has to be perform with bitwise NOT operation (ie, ~ operator) This patch clears current speed selection before writing the new speed settings to gmii2rgmii converter Signed-off-by: Fahad Kunnathadi <fahad.kunnathadi@dexceldesigns.com> Acked-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 14 September 2017, 13:14:42 UTC |
| a29aa21 | Kedareswara rao Appana | 12 September 2017, 12:55:39 UTC | net: macb: Fix issues with FPD off After suspend/resume with FPD off ethernet functionlaity is not working with the existing driver. This patch fixes this issue by implementing the context store in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 12 September 2017, 14:19:45 UTC |
| 223c3aa | Mubin Sayyed | 12 September 2017, 05:36:11 UTC | Revert "arm64: zynqmp: Enable smmu" Following issues are being observed when SMMU is enabled, - After suspend/resume with FPD off,all peripherals registered with SMMU are failed to work. - SATA device detection is failed Disabling SMMU till said issues are fixed. This reverts commit 3b94edc4c8aa7c6f07f99a52c1d85ad9e27d5ec0. Signed-off-by: Mubin Sayyed <mubinusm@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 12 September 2017, 07:47:26 UTC |
| bf76147 | Rajan Vaja | 28 August 2017, 09:13:57 UTC | ARM64: zynqmp: Do not set requirements to 0 for wakeup sources Devices which are set as wakeup source or belongs to wakeup source device's path should not be powered off by generic power domain driver. Add check in zynqmp GPD power off function to check if device is in wakeup source path. If so, set capabilities to WAKEUP instead of 0 in GPD power off function. Signed-off-by: Rajan Vaja <rajanv@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 12 September 2017, 07:45:47 UTC |
| aed8f55 | Kedareswara rao Appana | 08 September 2017, 14:30:47 UTC | dma: xilinx: Fix issues with vdma mulit fstore configuration This commit ie: 'commit 4f143cb03aba ("dmaeninge: xilinx_dma: Fix bug in multiple frame stores scenario in vdma")' fixes issues with multiple fstore by using circular mode feature. This implementation has a limitation as user needs to enable a hidden configuration option(c_debug_all) in the IP while creating the design. If user not aware of this h/w option and submits more frames then driver throughs a warning asking to enable the hidden configuration option. This patches fixes these issues by using the park mode feature. With this patch driver continuously parks through frame buffers based on the number of frames user submitted. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 12 September 2017, 07:45:47 UTC |
| f5e4ff5 | Hyun Kwon | 08 September 2017, 18:03:38 UTC | drm: xilinx: dp: Add delay after Monitor wake up Some monitors require delay to fully wake up. Otherwise, it may result in some error such as training failure. Delay of 4 msec was not specified in the spec, but found from experimentation (ex, no failure for 20 times or more). Thus, this setting is exposed as module parameter so that user can change if needed. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 12 September 2017, 07:45:46 UTC |
| f618d3b | Jeffrey Mouroux | 06 September 2017, 23:32:59 UTC | dma: xilinx: Add private API to permit retrieval of supported mem formats The video Framebuffer DMA IP requires clients to send a fourcc code to indicate the memory format layout. The IP can be configured to support a variety of memory formats ranging from YUYV, RGB and in either 8 bit or 10 bit formats. There has been no method for clients to obtain this list of supported formats. This patch adds private APIs that can be called from clients to retrieve this list so that user space applications can choose from any of the available memory formats. Depends on patch 13fd162 (dma: xilinx: Bug fix to ensure only video formats enabled in IP are in driver) Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 08 September 2017, 06:40:45 UTC |
| 5e0a3d2 | Hyun Kwon | 30 August 2017, 22:05:44 UTC | drm: xilinx: dp: Enable the training pattern transmission early Per DP v1.2 spec 3.5.1.2.2, the transmission of training pattern needs to be enabled before setting the sink device. This sequence was causing the failure of initial training attempt, thus, enable the pattern in the controller before setting the sink through aux. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 08 September 2017, 06:40:44 UTC |
| fec1fe4 | Manish Narani | 30 August 2017, 06:34:16 UTC | zynq: devicetree: Remove 'broken-adma2' property This patch removes 'broken-adma2' property from the zynq device-tree. This basically enables the use of ADMA instead of SDMA. With the latest kernel the ADMA is working fine in SD so no need to use the SDMA which is slower than ADMA. Fixed by : 7c415150cdd6 ("ARM: zynq: Reserve correct amount of non-DMA RAM") Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 05 September 2017, 12:21:47 UTC |
| 7858ca5 | Jeffrey Mouroux | 29 August 2017, 01:12:45 UTC | dma: xilinx: Bug fix to ensure GPIO is reset between DMA operations Some registers within the Video Framebuffer driver, such as the video format register, require a reset of the IP before they can be altered. Because there is no software accessible reset register, an external GPIO is used. This patch fixes a runtime issue wherein clients wish to reprogram the IP for a new memory between DMA operations. Without this fix, the Video Framebuffer Write IP may halt when a client requests a new DMA operation using a different memory format for writes to host memory. In some cases, Framebuffer Read operations will need to be reset when the downstream video pipeline is being reset. Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 05 September 2017, 12:21:46 UTC |
| 6f6aa29 | Saurabh Sengar | 29 August 2017, 06:32:57 UTC | drm: sdi: xilinx: correcting multi link payload value Channel bit have to be set only in case of multi link data. In SDI-TX logicore IP, except 3GB mode all other modes are single link only, hence these bit is redundant. 3GB mode is dual link. For 3GB mode first link have to be programmed as channel 1, and second link payload have to be programmed as channel 3. Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 04 September 2017, 13:01:01 UTC |
| 6edbe0d | Shubhrajyoti Datta | 29 August 2017, 09:40:53 UTC | clkc: zynqmp: fix the usb mux correct the offset for the usb mux. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 04 September 2017, 13:01:01 UTC |
| f8d41b7 | Mubin Sayyed | 31 August 2017, 05:56:06 UTC | arm64: zynqmp: Add back stream-id-cells property for lpd-dma stream-id-cells property is mandatory for SMMU driver over xen, so adding it back to all lpd-dma-channels. Since just removing "iommus" property suffice to bypass SMMU over native linux,SMMU would be still bypassed for lpd-dma over linux. Signed-off-by: Mubin Sayyed <mubinusm@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 04 September 2017, 12:14:45 UTC |
| 726f783 | Vishal Sagar | 01 September 2017, 05:48:58 UTC | v4l: xilinx: sdirxss: Add source change event support Add support for V4L2_EVENT_SOURCE_CHANGE event by generating this event when video lock occurs. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 04 September 2017, 07:04:06 UTC |
| 86888ff | Hyun Kwon | 02 September 2017, 01:05:48 UTC | drm: xilinx: plane: Don't cache the property values Some of these properties need to be updated as hardware values don't get restored to the default values. Thus, don't cache the values, but update those when there's request. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 04 September 2017, 07:04:05 UTC |
| 9f16845 | Manjukumar Matha | 29 August 2017, 15:03:27 UTC | mmu_defconfig: Enable devtmps and tmpfs Currently dropbear does not run in background because devtmps and tmpfs is not enabled by default. Enable devtmps and tmpfs to fix this issue Signed-off-by: Manjukumar Matha <manjukumar.harthikote-matha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 August 2017, 06:41:51 UTC |
| 6294bed | Anurag Kumar Vulisha | 29 August 2017, 15:53:21 UTC | dwc3: fix the logic for finding parent node The present logic doesn't fetch the correct parent node when two usb nodes are enabled. It searches all nodes and doesn't fetch the first node with matching compatible string when two usb nodes are enabled. This patch fixes the logic by searching "xlnx,zynqmp-dwc3" compatible string only in the parent nodes instead of the searching all nodes. Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 August 2017, 06:41:51 UTC |
| 158b600 | Michal Simek | 30 August 2017, 06:06:11 UTC | arm64: zynqmp: Add missing gpio property to dtsi All gpio controllers should contain this property. This property is not checked by the code that's why this issue wasn't found earlier. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 August 2017, 06:08:25 UTC |
| 45b0d9a | Tejas Prajapati Rameshchandra | 29 August 2017, 05:58:58 UTC | mtd: qspi: Corrected the sequence for accessing flash part For accessing flash part using the mtd devices for architectures which only supports 3 byte addressing need to call write_ear() for accessing memory above 16MB. After every call to write_ear(), write_enable() has to be called for further process. Signed-off-by: Tejas Prajapati Rameshchandra <tejaspra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 29 August 2017, 06:24:14 UTC |
| cba7215 | Vishal Sagar | 28 August 2017, 10:09:50 UTC | v4l: xilinx: sdirxss: Decode HD mode stream in case of no payload Get the stream properties even when no payload is obtained in HD mode. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 29 August 2017, 06:18:20 UTC |
| e506e84 | Jeffrey Mouroux | 28 August 2017, 21:56:54 UTC | Bug fix to ensure only video formats enabled in IP are in driver The driver used to assume that all IP supported video formats were legal choices for configuration. However, the IP can be configured to support all or only some (or only one) of the many possible formats. This patch adds the needed mechanism via device-tree to communicate to the driver which video formats are actually supported in the IP. Additional changes are required to ensure that DMA client requests for video formats that are NOT supported by the device instance are rejected. Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 29 August 2017, 06:15:00 UTC |
| eed0c52 | Jeffrey Mouroux | 28 August 2017, 21:56:53 UTC | Documentation: devicetree: bindings: dma: New dts property A new device tree property is described that will describe the video formats supported in the Video Framebuffer DMA device. The Video Framebuffer IP is configurabe and can be configured with varying support for a number of possible video memory formats in an effort to tailor the size of the logic footprint. The driver will utilize this new device tree property to describe this configuration. Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 29 August 2017, 06:15:00 UTC |
| 49026f2 | Jeffrey Mouroux | 28 August 2017, 21:56:52 UTC | dma: xilinx: Update to Framebuffer Driver to support dual addr pointers The 2017.3 version of the Video Framebuffer supports a separate address pointer for the chroma plane. This is needed when the chroma plane is not contiguous with the luma plane for semi-planar formats. This patch updates the client API as well. Additionally, the IP can be configured for either 32-bit or 64-bit DMA address pointers. A new device tree property is added which is used to indicate the address width and a callback is set during probe to write to memory using either 32-bit or 64-bit address formats depending on this dts property as well as the size of dma address space supported on the host. Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 29 August 2017, 06:14:59 UTC |
| 4e85058 | Jeffrey Mouroux | 28 August 2017, 21:56:51 UTC | Documentation: bindings: devicetree: dma: New compatible string and prop The Video Framebuffer driver will remove support for any v1 IP. The compatibility string associated with the v1 IP is described and the lack of future support indicated in the device tree bindings document. Additionally, for the v2 IP, the Video Framebuffer IP now supports either 32-bit or 64-bit dma address pointers which is indicated with a new required property. Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 29 August 2017, 06:14:59 UTC |
| 486d5f6 | Jeffrey Mouroux | 28 August 2017, 21:56:50 UTC | Documentation: bindings: devicetree: dma: Reformatted spaces to tabs The original device tree used 8 leading spaces in the example dts bindings. This change reformats these to tabs for proper indentation. Signed-off-by: Jeffrey Mouroux <jmouroux@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 29 August 2017, 06:14:58 UTC |
| 77cb786 | Mousumi Jana | 28 August 2017, 08:25:09 UTC | can: xilinx: fix runtime power management code This patch adds the fix for runtime power management. Without this the device usage counter decremented and device is going to suspend state.This patch resumes the device and prevents it from being suspended again. Signed-off-by: Mousumi Jana <mousumij@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 09:11:03 UTC |
| 820df1b | Vishal Sagar | 28 August 2017, 06:06:17 UTC | v4l: xilinx: sdirxss: Add support to decode 1080 line video in HD mode Adds support to decode 0x85 as byte1 in ST352 payload to detect 1080 line video. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 08:09:28 UTC |
| f0e5fae | Vishal Sagar | 28 August 2017, 06:06:16 UTC | v4l: xilinx: sdirxss: Add support to get width,height in SD mode Get the width & height in SD mode based on Transport stream family i.e. NTSC or PAL. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 08:09:28 UTC |
| 24ed4f9 | Vishal Sagar | 28 August 2017, 06:06:15 UTC | v4l: xilinx: sdirxss: Add support to decode more ST352 payloads for 3G mode Adds support to decode 0x88,0x89,0x8A,0x8B,0x8C byte1 from ST352 payload in 3G mode. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 08:09:27 UTC |
| 4258d83 | Vishal Sagar | 28 August 2017, 06:06:14 UTC | v4l: xilinx: sdirxss: Support decoding ST352 payload for 6G mode Patch adds support for decoding ST352 payload for 6G mode. It identifies if resolution is 4096x2160 or 3840x2160. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 08:09:27 UTC |
| 3c5133a | Vishal Sagar | 28 August 2017, 06:06:13 UTC | v4l: xilinx: sdirxss: Support decoding ST352 payload for 12G mode Patch adds support for decoding ST352 payload for 12G modes to identify if resolution is 4096x2160 or 3840x2160. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 08:09:26 UTC |
| b47af26 | Vishal Sagar | 28 August 2017, 06:06:12 UTC | v4l: xilinx: sdirxss: Get EDH status only in case of SD mode The EDH status registers are applicable only in SD mode. So EDH status related V4L controls check for current mode to be SD mode before accessing EDH status. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 08:09:26 UTC |
| 865daaa | Vishal Sagar | 28 August 2017, 06:06:11 UTC | v4l: xilinx: sdirxss: Don't register EDH controls if EDH not enabled in IP core Don't register the EDH related V4L controls when EDH processor is disabled in IP core settings. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 08:09:25 UTC |
| c4258bf | Vishal Sagar | 28 August 2017, 06:06:10 UTC | v4l: xilinx: sdirxss: Detect mode based on capability Set the mode detection based on IP configuration. If the IP is configured for 3G mode then don't allow detection for 6G and 12G Integral/Fractional modes. If the IP is configured for 6G mode then don't allow detection for 12G Integral/Fractional modes. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 08:09:25 UTC |
| edd5155 | Vishal Sagar | 28 August 2017, 06:06:09 UTC | v4l: xilinx: sdirxss: Fix kbuild warning of variable used without initalizing Fix warningi from kbuild test robot of variable being used without initializing. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 08:09:24 UTC |
| a5d7bad | Vishal Sagar | 28 August 2017, 06:06:08 UTC | v4l: xilinx: sdirxss: Update for new register spec This patch adds support in driver for new register spec finalized for SDI Rx Subsystem in 2017.3. Some bits from old registers are moved to new ones modifying the bit masks. Some old registers offsets have changed. Interrupt status register now has standard W1C behavior. Overflow/underflow interrupts are added. So removing V4L control and added events. Global interrupt enable register added. Soft reset bit is added to Reset Control Register. CRC Error Count register 31-16 exchanged with 15-0 with W1C behaviour. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 08:09:24 UTC |
| aff4deb | Leon Luo | 25 August 2017, 19:56:16 UTC | media: imx274 V4l2 driver for Sony imx274 CMOS sensor The imx274 is a Sony CMOS image sensor that has 1/2.5 image size. It supports up to 3840x2160 (4K) 60fps, 1080p 120fps. The interface is 4-lane MIPI running at 1.44Gbps each. This driver has been tested on Xilinx ZCU102 platform with a Leopard LI-IMX274MIPI-FMC camera board. Support for the following features: -Resolutions: 3840x2160, 1920x1080, 1280x720 -Frame rate: 3840x2160 : 5 – 60fps 1920x1080 : 5 – 120fps 1280x720 : 5 – 120fps -Exposure time: 16 – (frame interval) micro-seconds -Gain: 1x - 180x -VFLIP: enable/disable -Test pattern: 12 test patterns Signed-off-by: Leon Luo <leonl@leopardimaging.com> Tested-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 08:04:40 UTC |
| a5b8134 | Leon Luo | 25 August 2017, 19:56:17 UTC | dt: bindings: media: Add dt binding for imx274 The binding file for imx274 CMOS sensor V4l2 driver Signed-off-by: Leon Luo <leonl@leopardimaging.com> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 08:04:40 UTC |
| 345f126 | Soren Brinkmann | 25 August 2017, 21:11:04 UTC | arm64: zynqmp: Fix SD on zcu104 With a micro-sd interface, no write protect signal is available. Also, for SD to work the no-1-8-v property needs to be specified. Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 28 August 2017, 08:04:39 UTC |
| d0afb37 | Saurabh Sengar | 24 August 2017, 10:18:41 UTC | drm: xilinx: sdi: Adding more SD and 12G DRM modes Adding support for 720x480i@60, 3840x2160@60p and 3840x2160@50p Hz display modes Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 August 2017, 12:42:06 UTC |
| 901c909 | Saurabh Sengar | 24 August 2017, 06:18:58 UTC | drm: xilinx: sdi: adding st352 payload calculation for 4096 mode The 2048 bit need to be set for horizontal display lines of 4096 as well Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 August 2017, 12:42:06 UTC |
| 7d5ffbd | Saurabh Sengar | 23 August 2017, 13:35:18 UTC | drm: xilinx: sdi: replace SDI_MAX_DATASTREAM with actual number of channels No need to put payload in all the channels, but should be programmed only for the channels requested by user. Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 24 August 2017, 14:32:59 UTC |
| aa30213 | Srinivas Goud | 22 August 2017, 09:08:46 UTC | arm64: zynqmp: Update sd properties for dc5 This patch adds below properties to sd node for dc5 board dts -> no-1-8-v -> xlnx,mio_bank Signed-off-by: Srinivas Goud <srinivas.goud@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 24 August 2017, 14:32:58 UTC |
| 425c0ae | Hyun Kwon | 22 August 2017, 01:54:29 UTC | arm64: dts: zynqmp: Update the GPU address size The correct register size is 0x10000, otherwise it overlaps with other register space. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 24 August 2017, 14:32:58 UTC |
| f0d9d30 | Saurabh Sengar | 21 August 2017, 08:50:33 UTC | drm: xilinx: sdi: Adding transport support in st352 payload calculation Setting 7th bit of byte 2 as per st352 spec for 1125 vertical display. Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 24 August 2017, 14:32:57 UTC |
| ae8498d | Saurabh Sengar | 21 August 2017, 08:45:35 UTC | drm: xilinx: sdi: Adding 2048 support in st352 payload calculation Setting 6th bit of third byte if horizontal display is 2048. This is as per st352 spec for 2048 horizontal display. Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 24 August 2017, 14:32:57 UTC |
| fb9a8f7 | Saurabh Sengar | 21 August 2017, 07:11:44 UTC | drm: xilinx: sdi: correcting interlaced modes values Interlaced vertical line values should be half then progressive mode Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 24 August 2017, 14:32:56 UTC |
| 3b94edc | Naga Sureshkumar Relli | 31 July 2017, 05:22:08 UTC | arm64: zynqmp: Enable smmu This patch enables the smmu Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 21 August 2017, 10:52:13 UTC |
| 14a5392 | Michal Simek | 21 August 2017, 08:57:31 UTC | Revert "rtc: zynqmp: Disable module option in Kconfig" This reverts commit 00a16cc47f04a61c12b1d7896ea068c0c34e1157. Issue is fixed by previous commit. Resolution is when alarm timer registered module can't be unload. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 21 August 2017, 10:52:12 UTC |
| 281097a | Alexandre Belloni | 20 August 2017, 22:01:46 UTC | alarmtimer: ensure RTC module is not unloaded When registering the rtc device to be used to handle alarm timers, get_device is used to ensure the device doesn't go away but the module can still be unloaded. Call try_module_get to ensure the rtc driver will not go away. Reported-by: Michal Simek <monstr@monstr.eu> Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Tested-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 21 August 2017, 10:52:12 UTC |
| 5e5e895 | Saurabh Sengar | 12 August 2017, 14:08:36 UTC | drm: xilinx: sdi: Adding channel number in st352 payload Adding channel number in st352 payload. Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 21 August 2017, 07:01:56 UTC |
| ebbdeb2 | Edgar Lakis | 11 August 2017, 10:24:14 UTC | phy: zynqmp: Use the configured GT lane for tx_term_fix calibration This is a small correction to "phy: zynqmp: Change serdes calibraton logic to ICM_CFG1" (sha1: c1c13c82fbff75d1e4fb19b8ebfc27ea75656c2d) During the calibration process ICM_CFG register should be set to any valid lane. The previous version was using hardcoded setting of PCIe for lane 2 and 3. This breaks other devices on these lanes if they don't configure the phy in Linux (i.e. expect the value to be configured in FSBL). Current version will use the ICM_CFG value for the first selected phy instead of hardcoding lanes 2 and 3 to PCIe. Signed-off-by: Edgar Lakis <ela@phaseone.com> Acked-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:58:06 UTC |
| d136f7c | Soren Brinkmann | 18 August 2017, 00:18:14 UTC | v4l: xilinx-vpss-scaler: Fix phase calculation Fixes: ee7f2ef65107a65a1b9904b8d4ee4defbf16839a ("v4l: xilinx-vpss-scaler: driver support for xilinx vpss scaler" Cc: Rohit Athavale <RATHAVAL@xilinx.com> Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com> Tested-by: Rohit Athavale <rohit.athavale@xilinx.com> Reviewed-by: Rohit Athavale <rohit.athavale@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:12:20 UTC |
| 3003a94 | Hyun Kwon | 18 August 2017, 01:09:40 UTC | drm: xilinx: encoder: Check the encoder init function Check if the encoder slave driver registered the init callback. If the callback exists, the encoder driver assumes that the slave driver is ready to initialize. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:12:19 UTC |
| 3a49cee | Siva Rajesh | 17 August 2017, 07:33:01 UTC | drm: xilinx: dsi: Fixes the Hact calculation This patch fixes the HACT calculation. pixels-per-beat parameter is removed from parse_dt function. Signed-off-by: Siva Rajesh <siva.rajesh.jarugula@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:08:25 UTC |
| 60d3991 | Siva Rajesh | 17 August 2017, 07:33:02 UTC | dt: bindings: drm: xilinx: dsi: Correcting HACT calculations by removing the pixels-per-beat property HACT calculaion was incorrectly using the pixels-per-beat IP parameter. Since this is no longer used, hence removed. Signed-off-by: Siva Rajesh <siva.rajesh.jarugula@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:08:24 UTC |
| 00bf902 | Siva Rajesh | 17 August 2017, 07:33:00 UTC | drm: xilinx: dsi: Fix for checkpatch Fixed the checkpatch.pl warnings Signed-off-by: Siva Rajesh <siva.rajesh.jarugula@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:08:24 UTC |
| 89a7ff0 | Vishal Sagar | 16 August 2017, 11:14:09 UTC | v4l: xilinx: sdirxss: Initial support for getting video stream properties Initial support to get the video stream width, height and field (interlaced or progressive) based on the ST352 Data Stream 0 payload. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:08:23 UTC |
| eb81908 | Vishal Sagar | 16 August 2017, 11:14:08 UTC | v4l: xilinx: sdirxss: Add support for Video Unlock event This patch allows driver to generate a Video unlock event using which the application may stop streaming if required. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:08:22 UTC |
| 206948a | Vishal Sagar | 16 August 2017, 11:14:07 UTC | v4l: xilinx: sdirxss: Add V4L get controls for Modes, CRC, EDH and Video Bridge Status Added V4L controls for getting detected modes, CRC, EDH status and Video Bridge status. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:08:21 UTC |
| c9e6857 | Vishal Sagar | 16 August 2017, 11:14:06 UTC | v4l: xilinx: sdirxss: Add V4L control for Mode detection Mode detection V4L control added. Modes are passed as bitmask based on xilinx-sdirxss.h. If only one mode is selected then driver programs IP in Fixed mode else multi mode detection is enabled. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:08:21 UTC |
| fcf25ff | Vishal Sagar | 16 August 2017, 11:14:05 UTC | v4l: xilinx: sdirxss: Add V4L control for EDH error count This patch adds V4L control for enabling EDH counter. The list of masks for error conditions are added. It also fixes how the EDH Error counter register is set. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:08:20 UTC |
| a5c2d98 | Vishal Sagar | 16 August 2017, 11:14:04 UTC | v4l: xilinx: sdirxss: Add v4l control for Video Lock Window Add support for Video Lock Window control. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:08:20 UTC |
| 4eaea74 | Vishal Sagar | 16 August 2017, 11:14:03 UTC | v4l: xilinx: sdirxss: Add v4l control for Framer Add Framer control. The control can be set only if not streaming. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:08:19 UTC |
| 6147fea | Vishal Sagar | 16 August 2017, 11:14:02 UTC | v4l: xilinx: sdirxss: Streaming is enabled only on video lock Enable mode detection and start SDI Rx IP by default. The video bridges are enabled/disabled when starting/stopping streaming. Streaming is started only if video is locked. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:08:19 UTC |
| 5c64f19 | Vishal Sagar | 16 August 2017, 11:10:55 UTC | v4l: xilinx: sdirxss: Fix xsdirxss_core for kernel-doc Fix xsdirxss_core for kernel-doc Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:08:18 UTC |
| e06c2d8 | Vishal Sagar | 16 August 2017, 06:27:28 UTC | media: xilinx: cresample: Fix xilinx-v4l2-controls.h for checkpatch Fix checkpatch.pl --strict warnings for xilinx-v4l2-controls.h Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 18 August 2017, 12:08:18 UTC |
| 5b2dbde | Ravi Shankar Jonnalagadda | 08 August 2017, 09:58:07 UTC | PCI: ZYNQMP EP driver: Adding Root DMA support PS PCIe DMA can be configured to be both End Point or Root DMA This patch adds support for Root DMA. Signed-off-by: Ravi Shankar Jonnalagadda <vjonnal@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 August 2017, 13:51:16 UTC |
| 8028a0a | Ravi Shankar Jonnalagadda | 08 August 2017, 09:58:08 UTC | PCI: ZYNQMP PS PCIe Driver: Root DMA dt bindings Added device tree bindings for enabling root dma Signed-off-by: Ravi Shankar Jonnalagadda <vjonnal@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 August 2017, 13:51:16 UTC |
| 341a722 | Ravi Shankar Jonnalagadda | 08 August 2017, 09:58:06 UTC | PCI: ZYNQMP EP driver: Improving desc cleanup Using cached variable instead of data from buffer descriptor Signed-off-by: Ravi Shankar Jonnalagadda <vjonnal@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 August 2017, 13:51:15 UTC |
| e187719 | Ravi Shankar Jonnalagadda | 08 August 2017, 09:58:05 UTC | PCI: ZYNQMP EP driver: Fixed typo coaelse Fixed typo while declaring variable with name coalesce Signed-off-by: Ravi Shankar Jonnalagadda <vjonnal@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 August 2017, 13:51:14 UTC |
| c9d039e | Ravi Shankar Jonnalagadda | 08 August 2017, 09:58:04 UTC | PCI: ZYNQMP EP driver: Changing Register bit name Changing register bit name to convey more relevant information Signed-off-by: Ravi Shankar Jonnalagadda <vjonnal@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 August 2017, 13:51:14 UTC |
| 9ff333d | Ravi Shankar Jonnalagadda | 08 August 2017, 09:58:03 UTC | PCI: ZYNQMP EP driver: Minor code improvements Completed bytes and result variables can be declared only once as the values are assigned and cannot contain old values Signed-off-by: Ravi Shankar Jonnalagadda <vjonnal@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 August 2017, 13:51:13 UTC |
