| c2ba891 | Harini Katakam | 07 June 2018, 09:13:23 UTC | arm64: zynqmp: Enable GMII2RGMII driver in ZynqMP defconfig Enable Xilinx GMII2RGMII converter driver in defconfig Signed-off-by: Harini Katakam <harini.katakam@xilinx.com> Acked-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu> | 07 June 2018, 11:00:15 UTC |
| d937ecc | Harini Katakam | 07 June 2018, 08:07:02 UTC | phy: gmii2rgmii: Add check for external phy driver Add a check for external phy driver to be probed before dereferencing phy driver pointer. This fixes the following crash: [ 2.439334] libphy: MACB_mii_bus: probed [ 2.444797] Unable to handle kernel NULL pointer dereference at virtual address 00000000 [ 2.452689] Mem abort info: [ 2.455453] Exception class = DABT (current EL), IL = 32 bits [ 2.461334] SET = 0, FnV = 0 [ 2.464361] EA = 0, S1PTW = 0 [ 2.467474] Data abort info: [ 2.470325] ISV = 0, ISS = 0x00000005 [ 2.474135] CM = 0, WnR = 0 [ 2.477077] [0000000000000000] user address but active_mm is swapper [ 2.483392] Internal error: Oops: 96000005 1 SMP [ 2.488232] Modules linked in: [ 2.491261] CPU: 3 PID: 1 Comm: swapper/0 Not tainted 4.14.0-xilinx-v2018.2 #1 [ 2.498438] Hardware name: ZynqMP ZC1275 RevB (DT) [ 2.503196] task: ffffffc06d846d00 task.stack: ffffff8008038000 [ 2.509085] PC is at __memcpy+0x100/0x180 [ 2.513061] LR is at xgmiitorgmii_probe+0x7c/0xf0 Signed-off-by: Harini Katakam <harini.katakam@xilinx.com> Signed-off-by: Michal Simek <monstr@monstr.eu> | 07 June 2018, 11:00:15 UTC |
| 047a00b | Michal Simek | 29 May 2018, 13:28:43 UTC | arm64: zynqmp: Fix address for tca6416_u97 chip on zcu104 I2c address is not 0x21 but 0x20. This patch is fixing both revA and revC boards. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 May 2018, 06:03:31 UTC |
| e648c3b | Michal Simek | 23 May 2018, 06:15:27 UTC | xilinx: Enabled sdfec driver in defconfig Enable this driver in default xilinx defconfig. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 May 2018, 06:25:21 UTC |
| c674c2d | Tejas Prajapati Rameshchandra | 08 May 2018, 06:09:01 UTC | mtd: spi-nor: Update erasesize if dual parallel configuration For UBIFS we are using 64KB erase size that becomes 128KB for dual parallel configuration. With the introduction of SFDP the erase size is not updating as expected for dual parallel configuration. This patch updates the erase size in dual parallel configuration. Signed-off-by: Tejas Prajapati Rameshchandra <tejas.prajapati.rameshchandra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 22 May 2018, 14:23:17 UTC |
| 125f1b1 | David Cater | 15 May 2018, 21:37:52 UTC | clk: Add ccf driver for IDT 8T49N24x UFT This is a common clock framework driver that supports the 8T49N241 chip. No other chips in the family are currently supported. The driver supports setting the rate for all four outputs on the chip and automatically calculating/setting the appropriate VCO value. The driver can read a full register map from the device tree, and will use that register map to initialize the attached part (via I2C) when the system boots. Any configuration not supported by the common clock framework must be done via the full register map, including optimized settings. All outputs are currently assumed to be LVDS, unless overridden in the full register map in the DT. Signed-off-by: David Cater <david.cater@idt.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 21 May 2018, 06:30:29 UTC |
| a84dbe4 | David Cater | 15 May 2018, 21:36:52 UTC | dt-bindings: Add binding for IDT 8T49N24x UFT IDT8T49N241 has 4 outputs; 1 integral divider and 3 fractional dividers. The 8T49N241 accepts up to two differential or single-ended input clocks and a fundamental-mode crystal input. The internal PLL can lock to either of the input reference clocks or just to the crystal to behave as a frequency synthesizer. Signed-off-by: David Cater <david.cater@idt.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 21 May 2018, 06:30:29 UTC |
| f8ff267 | Michael Gill | 15 May 2018, 20:13:56 UTC | staging: apf: Correct sg list length assignment in apf dma When using DMABUFs in the apf dma driver, there were specific lengths that resulted in the transfer length being incorrectly assigned. This patch corrects that by assigning lengths correctly when the sg descriptor length is smaller than the transfer size. Signed-off-by: Michael Gill <michael.gill@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 16 May 2018, 07:56:27 UTC |
| c3ad4b9 | Tejas Prajapati Rameshchandra | 15 May 2018, 12:37:17 UTC | spi: spi-zynqmp-gqspi: use dma mode only if the buffer is not vmalloced As per the kernel documentation the buffer to be used with dma should not be vmalloced due to the fact that if buffer is vmalloced then page entries are not consistent in physical pages. That would lead to failure cases in dma. This patch adds condition to check if the buffer to be read is vmalloced or not if not vmalloced then uses dma mode otherwise io mode. Signed-off-by: Tejas Prajapati Rameshchandra <tejas.prajapati.rameshchandra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 May 2018, 15:22:33 UTC |
| f3d40d3 | Derek Kiernan | 15 May 2018, 00:17:02 UTC | misc: xilinx-sdfec: Correct write to protect regs The function xsdfec_wr_protect incorrectly skips writing to the CODE_WR_PROTECT and AXI_WR_PROTECT registers when the input argument wr_pr is false. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 May 2018, 15:22:33 UTC |
| e5b6542 | Derek Kiernan | 15 May 2018, 00:17:01 UTC | misc: xilinx-sdfec: Correct write to AXIS_WIDTH reg The function xsdfec_cfg_axi_streams incorrectly calls xsdfec_translate_axis_words_cfg_val when calculating the value for din_width_field. This can result in a incorrect write to AXIS_WIDTH register. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 May 2018, 15:22:33 UTC |
| 672ffb4 | Derek Kiernan | 15 May 2018, 00:17:00 UTC | misc: xilinx-sdfec: Remove RESET_REQ IOCTL No longer needed the functionality is implemented in SET_DEFAULT_CONFIG and CLEAR_STATS ioctl as reset occurs external to the driver. No reset function implemented. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 May 2018, 15:22:33 UTC |
| 74b7976 | Derek Kiernan | 15 May 2018, 00:16:59 UTC | misc: xilinx-sdfec: Add SET_DEFAULT_CONFIG IOCTL Typically this IOCTL is used after the SD-FEC has been reset to ensure the SD-FEC returns to it's default configuration. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 May 2018, 15:22:33 UTC |
| 7631d68 | Derek Kiernan | 15 May 2018, 00:16:58 UTC | misc: xilinx-sdfec: Add GET_STATS IOCTL Allows the user to retrieve error stats collected during interrupts. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 May 2018, 15:22:33 UTC |
| 60727d9 | Derek Kiernan | 15 May 2018, 00:16:57 UTC | misc: xilinx-sdfec: Add CLEAR_STATS IOCTL Allows the user to clear error stats collected during interrupts. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 May 2018, 15:22:33 UTC |
| 5bf8ce6 | Derek Kiernan | 15 May 2018, 00:16:56 UTC | misc: xilinx-sdfec: add_ldpc incorrectly sets code The function xsdfec_add_ldpc incorrectly sets the code as LDPC. This value should only be set during the probe function. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 May 2018, 15:22:33 UTC |
| 8155bf1 | Derek Kiernan | 15 May 2018, 00:16:55 UTC | misc: xilinx-sdfec: Remove tracking of table entries For the SC, LA and QC Tables software tracked the offset of last written entry to ensure no overwriting, using sc_off, qc_off and la_off from struct xsdfec_dev. This assumes contiguous writing and no updating of the tables, which restricts the use cases of the SD-FEC, e.g. updating existing entries for a code. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 May 2018, 15:22:33 UTC |
| 795d614 | Derek Kiernan | 15 May 2018, 00:16:54 UTC | misc: xilinx-sdfec: Fix AXIS_ENABLE_MASK value The AXIS_ENABLE register has 6 bits not 5, change value of AXIS_ENABLE_MASK from 0x1f to 0x3f. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 15 May 2018, 15:22:33 UTC |
| 7b2c496 | Derek Kiernan | 11 May 2018, 09:38:01 UTC | misc: xilinx-sdfec: Updated DT update implementation To align with the device tree entry updates for sd-fec-1.1 the following changes have been implemented. - Changed the xsdfec_of_match compatible string. - Updates the driver to read, store and configure the AXI Stream interfaces. - Removes reading op-mode DT property. - remove unused op-mode member from xsdfec_config. - reads of the following Device Tree properties and sets the AXIS_WIDTH register. - din-words. - din-width. - dout-words. - dout-width. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 May 2018, 13:45:41 UTC |
| e247d42 | Derek Kiernan | 11 May 2018, 09:38:00 UTC | misc: xilinx-sdfec: Add new version DT binding file Introduces a new DT binding file as compatibility is broken with previous version by introducing the following changes to the DT properties. - Updates the compatible string to sd-fec-1.1. - Removes the op-mode property. - Adds mandatory AXI Stream propterties. - din-words. - din-width. - dout-words. - dout-width. Also specifies interrupt as an optional property. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 May 2018, 13:45:41 UTC |
| 4140b0f | Derek Kiernan | 11 May 2018, 09:37:59 UTC | misc: xilinx-sdfec: Use xsdfec_config in xsdfec Avoids copying the variables in function xsdfec_get_config, e.g. for ioctl XSDFEC_GET_CONFIG. Also removed state from xsdfec_config as this aligns better with GET_STATUS ioctl rather than GET_CONFIG. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 May 2018, 13:45:41 UTC |
| 73ef385 | Bharat Kumar Gogada | 10 May 2018, 12:59:23 UTC | PCI: XDMA PL PCIe: Add support MSI DECODE mode The XDMA IP now support MSI decode mode along with existing MSI FIFO mode. In both FIFO and DECODE mode 64 MSI's are supported. The new DECODE mode uses three GIC IRQ lines, one for legacy and error, two for lower and upper 32 MSI. Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 May 2018, 13:45:41 UTC |
| 3609078 | Bharat Kumar Gogada | 10 May 2018, 12:59:22 UTC | PCI: XDMA PL PCIe: Add documentation for MSI DECODE mode. The XDMA IP now support MSI decode mode along with existing MSI FIFO mode. The new DECODE mode uses three GIC IRQ lines, one for legacy and error, two for lower and upper 32 MSI. Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 May 2018, 13:45:41 UTC |
| 825ebfc | Bharat Kumar Gogada | 10 May 2018, 12:59:21 UTC | PCI: XDMA PL PCIe: Fix Multi MSI data programming Devices requesting multiple MSI, message data being programmed is modified by device. Avoid modified message data falling into another device data range. Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 May 2018, 13:45:41 UTC |
| dd7918d | Venkateshwar Rao Gannavarapu | 10 May 2018, 10:06:11 UTC | drm: xlnx: pl_disp: fix vblank time out issue This patch adds a vblank processing delay to avoid timeout in processing the first frame. Signed-off-by: Venkateshwar Rao Gannavarapu <venkateshwar.rao.gannavarapu@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 10 May 2018, 12:23:48 UTC |
| 1a8900f | Venkateshwar Rao Gannavarapu | 07 May 2018, 07:43:39 UTC | drm: xlnx: mixer: Update planes asynchronously in the legacy entry This patch makes the plane update asynchronous to vsync and handles format changes. Signed-off-by: Venkateshwar Rao Gannavarapu <venkateshwar.rao.gannavarapu@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Tested-by: Anil Kumar Mamidala <amamidal@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 09 May 2018, 09:03:01 UTC |
| 2e77607 | Satish Kumar Nagireddy | 05 May 2018, 00:31:24 UTC | xilinx: v4l2: dma: Add multiple output support The current implementation supports single direction which can be input or output. The requirement is to support multiple output DMAs, for example Source -> split -> scaler -> dma0 |-> scaler -> dma1 This patch walks through the graph starting from each of dma and enable/disable subdevs only once in case if they are shared between subgraphs. Signed-off-by: Satish Kumar Nagireddy <satish.nagireddy.nagireddy@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 09 May 2018, 08:44:19 UTC |
| dd74abb | Vishal Sagar | 02 May 2018, 12:38:44 UTC | v4l: xilinx: dma: Terminate DMA when media pipeline fails to start If an incorrectly configured media pipeline is started, the allocated dma descriptors aren't freed. This leads to kernel oops when pipeline is configured correctly and run subsequently. This patch fixes this issue by freeing the descriptors on media pipeline start failure. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Tested-by: Anil Kumar Mamidala <amamidal@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 03 May 2018, 05:52:36 UTC |
| 59e8b54 | Naga Sureshkumar Relli | 28 April 2018, 03:34:58 UTC | mtd: nand: pl35x: Fix incorrect ooblayout offset update ooblayout64_ecc offset and free area updates are incorrect. This patch fixes this and also updates the ecc code. Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 April 2018, 07:18:07 UTC |
| f479cb5 | Radhey Shyam Pandey | 27 April 2018, 10:12:48 UTC | dmaengine: xilinx: dma: In axidma add support for 64MB data transfer In 2018.1 axidma IP support for 64 MB data transfer is added by increasing buffer length width to 26bit. Modify DT "xlnx,sg-length-width" validation accordingly. Since max length for previous IP version is 23 bit display a warning message if length is in 23-26 bit range. It would have an ideal solution to add a separate compatibility string and config structure for this changed IP but due to lack of proper DMA IP versioning it's dropped. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 April 2018, 07:13:22 UTC |
| b5f0958 | Radhey Shyam Pandey | 27 April 2018, 10:12:49 UTC | dt-bindings: dmaengine: xilinx_dma: In axidma add support for 64MB data transfer Modify xlnx,sg-length-width description to be inline with implementation. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 April 2018, 07:13:22 UTC |
| 6470990 | Shubhrajyoti Datta | 24 April 2018, 07:08:14 UTC | fpga: Add AFI config driver Add a AFI config driver. This is useful for the PS to PL configuration for the fpga manager. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 April 2018, 07:13:22 UTC |
| 41f5c09 | Shubhrajyoti Datta | 24 April 2018, 07:08:15 UTC | fpga: doc: Add binding doc for the afi config driver Add the binding document for the afi config driver. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 April 2018, 07:13:22 UTC |
| ecc3314 | Vishal Sagar | 27 April 2018, 08:26:56 UTC | dma: xilinx: Add fid property for interlaced support in framebuffer Add support for new property xlnx,fid which is present when IP configured to support interlaced video. The Field ID bit access is gated based on the presence of this property. This is an optional property. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 April 2018, 07:13:22 UTC |
| 67ada1c | Vishal Sagar | 27 April 2018, 08:26:55 UTC | dt-bindings: dma: Add fid property for interlaced video Add a new property which should be present if framebuffer is used to handle interlaced video. Access to Field ID bit in IP is gated based on this property. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 April 2018, 07:13:22 UTC |
| 699b419 | Vishal Sagar | 26 April 2018, 18:48:40 UTC | dma: xilinx: Flush the framebuffer FIFO on halt On framebuffer halt, set the flush bit of control register and wait for the flush status bit to be set which indicates the framebuffer FIFO is flushed. It waits for a maximum of 50 ms time for flush to happen. This is done after framebuffer is stopped and all pending transactions are done i.e. idle state is reached. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 April 2018, 07:13:22 UTC |
| a868bf0 | Hyun Kwon | 26 April 2018, 22:00:57 UTC | drm: xlnx: zynqmp: Update planes asynchronously in the legacy entry With the atomic modesetting, the legacy APIs create a commit for single change. This serializes each changes with vsync interval as each commit is synchronous to vsync. So, if application is changing both crtc and plane within single vsync interval, only one will be taken in a single interval, and it gives half of the framerate. This patch makes the plane update asynchronous to vsync, meaning the plane update from the legacy set plane API happens immediately when there's no atomic commit queued for the given plane. The implementation is based on drm_atomic_helper_update_plane() but enables the async update. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Tested-by: Tejas Upadhyay <tejas.upadhyay@xilinx.com> Tested-by: Devarsh Thakkar <devarsht@xilinx.com> Tested-by: Preetesh Parekh <preetesh@xilinx.com> Reviewed-by: Satish Kumar Nagireddy <satishna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 30 April 2018, 07:13:22 UTC |
| 16a6651 | Naga Sureshkumar Relli | 26 April 2018, 10:00:21 UTC | spi: zynqmp: Fix for qspi dma when accessing address space beyond 32-bit dma_set_mask should be called before registering to spi_master. In the current flow dma_set_mask is set to 44 bit but after registering to spi_master. because of this, qspi dma is not able to access beyond 32-bit address space. during spi_register_master, core will do some dma transfers, hence not able to access beyond 32-bit address space. Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2018, 14:32:20 UTC |
| 7e8d9f8 | Anurag Kumar Vulisha | 26 April 2018, 07:19:17 UTC | usb: dwc3: gadget: ISOC transfers should be stopped before starting a transfer For ISOC transfers the requests are not queued until the HOST requests for data and XferNotReady event is generated .But XferNotReady event is not getting generated for ISOC transfers for the second time after Endpoint configuration. Since ISOC packets depend on the XferNotReady events, they will not be queued to controller. Because of this issue timeout happens on the application layer. This patch fixes this issue by issuing END TRANSFER command before starting any ISOC transfers. Doing so will make the controller clear the previous allocated endpoint resources and reallocate resources when the transfer is requested. Because of this change XferNotReady events will be generated when host requests for the ISOC transfer. Signed-off-by: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2018, 14:32:20 UTC |
| 4aeaea5 | Dhaval Shah | 26 April 2018, 07:00:31 UTC | soc: xilinx: vcu: Optimize the VCU PLL calculation. Calculate the maximum and minimum possible FBDIV values so that number of iteration can be reduce to calculate FBDIV and divisor for the provided clock information. Signed-off-by: Dhaval Shah <dhaval.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 April 2018, 14:32:20 UTC |
| ad0d895 | Vishal Sagar | 23 April 2018, 12:14:23 UTC | v4l: xilinx: dma: Add interlaced support This patch adds interlaced support to the Xilinx V4L dma client. In case of capture pipeline, the field id is read from the callback. A check is present to find and correct sequence number in case a frame is dropped i.e. fid is repeated. For this the prev_fid member is used to store the previous fid value to be compared with one returned. In case of output pipeline, the field id is set per dma descriptor. A dma descriptor pointer is added to xvip_dma_buffer so that it may be passed as a reference while getting the fid. The video node gets the field type of the subdev prior and checks if it is of V4L2_FIELD_ALTERNATE type. If yes then height is halved. Some other minor fixes for checkpatch are also applied here. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 April 2018, 13:46:30 UTC |
| 1474437 | Derek Kiernan | 25 April 2018, 11:18:54 UTC | misc: xilinx-sdfec: Improve the IOCTL Handling Use the IOCTL Macros provided by Linux Kernel when handling IOCTL requests. Plus for all parameter passing for IOCTL commands use pointers to be consistent. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 April 2018, 13:40:43 UTC |
| 2e5a707 | Derek Kiernan | 25 April 2018, 11:18:53 UTC | misc: xilinx-sdfec: Use "code_id" to dev_err calls code_id is a multiplier used when calculating the reg_addr in existing dev_err calls in the following functions: - xsdfec_collect_ldpc_reg0 - xsdfec_collect_ldpc_reg1 - xsdfec_collect_ldpc_reg2 - xsdfec_collect_ldpc_reg3 Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 April 2018, 13:40:43 UTC |
| 4d16f52 | Derek Kiernan | 25 April 2018, 11:18:52 UTC | misc: xilinx-sdfec: Remove Max Device Limitation Removed the limitation as number of devices may vary in the future. Signed-off-by: Derek Kiernan <derek.kiernan@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 April 2018, 13:40:43 UTC |
| 942988d | Rajan Vaja | 25 April 2018, 12:34:04 UTC | arm64: zynqmp: Add TTC clocks PS clock(LPD_APB_CLK) is default clock for TTC. Add this clock entry in TTC nodes. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 April 2018, 13:29:14 UTC |
| 3789e5e | Dhaval Shah | 25 April 2018, 07:46:07 UTC | soc: xilinx: vcu: Divisor calculation for MCU clock is updated. Divisor of the mcu clock is calculated in such a way that mcu clock derived from the calculation is greater than or equal to provided values from the logicoreIP. Signed-off-by: Dhaval Shah <dhaval.shah@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 April 2018, 12:27:12 UTC |
| f805b07 | Vishal Sagar | 24 April 2018, 05:08:04 UTC | dma: xilinx: Get DMA alignment from device tree for Framebuffer Patch adds xlnx,pixels-per-clock(ppc) and xlnx,dma-align device tree property decoding to calculate the required DMA alignment. xlnx,pixels-per-clock is mandatory property now. Minimum alignment required is 8 * pixels per clock in bytes. dma-align property is optional. In case present, dma-align must be a power of 2 and be >= 8 * ppc. If absent, alignment is set as ppc * 8. Added a new compatible string and structure which contains dma direction and flag. The flag would be a bitmask of properties. When ever a new IP or device tree property is to be supported, a bitmask for the same is to be created and added to this flag. For the new v2.1 compatible string, a new XILINX_PPC_PROP bitmask is set in the flags. If the flag is set then, pixels-per-clock property would be checked. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Radhey Shyam Pandey <radheys@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 April 2018, 07:24:27 UTC |
| 0f1ec15 | Vishal Sagar | 24 April 2018, 05:08:03 UTC | Documentation: devicetree: bindings: dma: Add properties for DMA alignment Adds the pixels per clock and dma-align device tree properties. These are used to determine the DMA memory alignment. New compatible strings xlnx,axi-frmbuf-rd-v2.1 and xlnx,axi-frmbuf-wr-v2.1 have also been added for this. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Radhey Shyam Pandey <radheys@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 April 2018, 07:24:27 UTC |
| 16c2f51 | Vishal Sagar | 24 April 2018, 17:57:15 UTC | dma: xilinx: Add alpha formats support for Framebuffer Read Add support to translate alpha DRM fourcc formats to corresponding 8bpc alpha color formats supported by the Framebuffer Read IP. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 April 2018, 07:07:31 UTC |
| 91f7522 | Vishal Sagar | 24 April 2018, 17:57:14 UTC | Documentation: devicetree: bindings: dma: Add alpha formats Update the documentation to add support for the alpha formats supported by Framebuffer Read IP. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 April 2018, 07:07:31 UTC |
| f18d4e4 | Manish Narani | 23 April 2018, 06:28:07 UTC | sdhci: arasan: Remove quirk for broken base clock This patch removes quirk which indicates a broken base clock. This was making the kernel report wrong base clock of ~187MHz instead of 200MHz even as the measurement on the hardware was showing 200MHz. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 98ce4fa | Shubhrajyoti Datta | 20 April 2018, 11:20:52 UTC | tty: uartlite: Enable clocks at probe At probe the uartlite is getting configured. Enable the clocks before assiging uart and disable after probe is done. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 8069fd3 | Shubhrajyoti Datta | 20 April 2018, 11:23:48 UTC | tty: uartlite: Update the clock name Update the clock name to match the IP documentation. Also document the same in bindings. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 7e719b9 | Rajan Vaja | 19 April 2018, 18:13:11 UTC | firmware: zynqmp: Add sysfs and IOCTL to set boot health status Add sysfs interface to set boot health status from userspace. Add IOCTL ID used by this interface to communicate with firmware. If PMUFW is compiled with CHECK_HEALTHY_BOOT, it will check the healthy bit on FPD WDT expiration. If healthy bit is set by a user application running in Linux, PMUFW will do APU only restart. If healthy bit is not set during FPD WDT expiration, PMUFW will do system restart. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 90e8daa | Hyun Kwon | 19 April 2018, 21:00:21 UTC | sound: xilinx: pcm: Set the shorter device name By default, the device names derive from the dt description. The DP pcm devices are represented as a child node of DP node, which results in both parent and child node names in the device name. The name created in this way gets too long to fit into the sound component name, and last characters where IDs are located are not included. This gives the same component name for two different components, and the debugfs fails to create entries with same name as warning below: xilinx-dp-snd-pcm fd4a0000.zynqmp-display:zynqmp_dp_snd_pcm1: ASoC: Failed to create component debugfs directory This fixes it by setting the child node name as a device name. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Satish Kumar Nagireddy <satishna@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| f3bcb86 | Hyun Kwon | 11 April 2018, 16:36:33 UTC | drm: xlnx: fb: Prefer the current format depth over depth from fb helper The drm fb helper has specific preference of bpp and depth. For example, for 32bit bpp, the depth is hard-coded to be 24. If it's not aligned with the supported format of a drm device, it fails to initialize fbdev. So override the depth value from fb helper with the current format of the drm device. This will allow to initialize the fbdev with preferred format that matches with actual format. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Saurabh Sengar <saurabhs@xilinx.com> Tested-by: Anil Kumar Mamidala <amamidal@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| f7225b8 | Manish Narani | 12 April 2018, 12:30:34 UTC | sdhci: arasan: Add runtime PM support This patch adds runtime PM support in Arasan SD driver. Signed-off-by: Manish Narani <manish.narani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 4c778ce | Tejas Prajapati Rameshchandra | 10 April 2018, 10:44:37 UTC | spi: spi-xilinx: passed correct structure in pm calls. Added device structure in xspi structure and cached &pdev->dev in it for use with pm_runtime_get_sync in driver. Signed-off-by: Tejas Prajapati Rameshchandra <tejaspra@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 277956e | Rohit Athavale | 05 April 2018, 17:20:33 UTC | dt-bindings: display: xlnx: mixer: Update example to fix format strings This commit updates the color formats for the example. Signed-off-by: Rohit Athavale <rohit.athavale@xilinx.com> Reviewed-by: Saurabh Sengar <saurabhs@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 8ca6e40 | Rohit Athavale | 05 April 2018, 17:20:32 UTC | dt-bindings: display: xlnx: mixer: Add supported formats table This commit adds a list of supported formats that the driver supports. Signed-off-by: Rohit Athavale <rohit.athavale@xilinx.com> Reviewed-by: Saurabh Sengar <saurabhs@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| edcaf87 | Fengguang Wu | 10 April 2018, 18:11:47 UTC | drm: xlnx: pl_disp: fix odd_ptr_err.cocci warnings PTR_ERR should normally access the value just tested by IS_ERR Generated by: scripts/coccinelle/tests/odd_ptr_err.cocci Fixes: 742243a44a73 ("drm: xlnx: pl_disp: Use xlnx pipeline calls") CC: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Julia Lawall <julia.lawall@lip6.fr> Reviewed-by: Saurabh Sengar <saurabhs@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 732e12b | Shubhrajyoti Datta | 04 April 2018, 12:29:26 UTC | usb: gadget: udc-xilinx: Add clock support Currently the driver depends on the bootloader to enable the clocks. Add support for clocking. The patch enables the clock at probe and disables them at remove. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 0c03e59 | Shubhrajyoti Datta | 04 April 2018, 12:29:25 UTC | doc: binding: Add clock support Add clock support for xilinx udc driver. While at it fix the case for xlnx,has-builtin-dma. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 3551688 | Glenn Langedock | 27 March 2018, 14:09:25 UTC | gpio: zynq: protect direction in/out with a spinlock Fix race condition when changing the direction (in/out) of the GPIO pin. The read-modify-write sequence (as coded in the driver) isn't atomic and requires synchronization (spinlock). Signed-off-by: Glenn Langedock <Glenn.Langedock@barco.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 92c1378 | Manish Narani | 15 March 2018, 09:26:39 UTC | iio: adc: xilinx-ams: Modify driver to match AMS standard sequence This patch modifies the driver flow to match with the standard AMS sequence. Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 8a4e8d6 | Michal Simek | 27 March 2018, 12:31:42 UTC | arm: zynq: Remove 0x prefixes from cc108 The patch fixing issues reported by DTC: arch/arm/boot/dts/zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0x400000 unit name should not have leading "0x" arch/arm/boot/dts/zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0x800000 unit name should not have leading "0x" arch/arm/boot/dts/zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0xc00000 unit name should not have leading "0x" arch/arm/boot/dts/zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0xd00000 unit name should not have leading "0x" arch/arm/boot/dts/zynq-cc108.dtb: Warning (unit_address_format): Node /amba/spi@e000d000/flash@0/partition@0xf00000 unit name should not have leading "0x" Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 1b6d237 | Michal Simek | 27 March 2018, 11:48:51 UTC | arm: zynq: Fix eeprom dt nodes - Use eeprom for node name - Use atmel compatible string instead of at. - Add missing labels Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 9a24d44 | Michal Simek | 27 March 2018, 11:49:05 UTC | arm: zynq: Use fixed partitions for spi flash for zc770 xm010 Sync with mainline. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| c0ee7a8 | Michal Simek | 27 March 2018, 11:43:05 UTC | arm: zynq: Sync up licenses with mainline kernel Use different location for SPDX line. Also update dates for new mainline DTS files. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 9f5f73e | Javier Martinez Canillas | 15 June 2017, 18:54:12 UTC | ARM: dts: zynq: Add generic compatible string for I2C EEPROM The at24 driver allows to register I2C EEPROM chips using different vendor and devices, but the I2C subsystem does not take the vendor into account when matching using the I2C table since it only has device entries. But when matching using an OF table, both the vendor and device has to be taken into account so the driver defines only a set of compatible strings using the "atmel" vendor as a generic fallback for compatible I2C devices. So add this generic fallback to the device node compatible string to make the device to match the driver using the OF device ID table. Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 5d21d76 | Michal Simek | 17 January 2018, 14:21:38 UTC | arm: zynq: Add missing address node name in microzed board This patch is fixing issue reported by dtc: arch/arm/boot/dts/zynq-microzed.dtb: Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| e91db93 | Michal Simek | 06 February 2018, 13:00:30 UTC | arm: zynq: Use i2c-mux instead of i2cswitch for pca9548 i2c muxes should described like this. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 26dc33f | Manish Narani | 27 March 2018, 10:06:30 UTC | dt: bindings: Add AMS channels details This patch adds details of AMS channels to the Device Tree binding documentation. Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| ff4f94e | Michal Simek | 27 March 2018, 11:09:15 UTC | arm64: zynqmp: Fix spi flash partition definition for zc1751 dc2 Using different node name and label partitions as data. Also use latest compatible strings based on mainline review. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 0463556 | Michal Simek | 27 March 2018, 11:15:17 UTC | arm64: zynqmp: Add eeprom reference to eeprom nodes Eeprom can contain information which can be used by nvmem drivers. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 97b808c | Michal Simek | 27 March 2018, 10:53:37 UTC | arm64: zynqmp: Use backward compatible string for gem Add backward compatible string for gem ("cdns,gem"). Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| ce596e1 | Michal Simek | 27 March 2018, 10:50:04 UTC | arm64: zynqmp: Use s/_/-/g in node name for zcu102 rev1.0 Follow spec for node names. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 87b3d6c | Michal Simek | 27 March 2018, 10:48:30 UTC | arm64: zynqmp: Add silabs prefix to u69 for zcu102 Add vendor prefix to si5341. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| d9559c3 | Michal Simek | 27 March 2018, 10:31:53 UTC | arm64: zynqmp: Use wifi as node name for wl1831 for zcu100 Use standard name for wifi node. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 9feef81 | Michal Simek | 27 March 2018, 10:29:38 UTC | arm64: zynqmp: Use 96boards labels for zcu100 Use label for i2c and spi buses. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 14607d1 | Michal Simek | 27 March 2018, 10:27:43 UTC | arm64: zynqmp: Sync up pmic with mainline for zcu100 pmic should use pmic as node name. Also remove comments about setting. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 4afbd2a | Michal Simek | 27 March 2018, 11:00:40 UTC | arm64: zynqmp: Remove double spaces from dts files There is no reason to have double spaces for indentation. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| e89beb9 | Michal Simek | 27 March 2018, 10:01:24 UTC | arm64: zynqmp: Remove additional comments from dts files Remove additional comments which were removed as the part of upstreaming. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| ce7d968 | Michal Simek | 27 March 2018, 10:13:13 UTC | arm64: zynqmp: Use keycode from input/input.h zcu100 could use sw4 as key_power instead of key_down. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 3a74c41 | Michal Simek | 27 March 2018, 10:05:38 UTC | arm64: zynqmp: Label 8T49n287 as clock-generator Based on spec clock chips should be labeled as clock-generators. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 9dc6d3f | Michal Simek | 27 March 2018, 10:04:14 UTC | arm64: zynqmp: Enable watchdog on zcu106 It is enabled in mainline that's why enable it here too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 8756cb5 | Michal Simek | 27 March 2018, 08:54:25 UTC | arm64: zynqmp: Use atmel prefix instead of at This changes was done in mainline and this patch is just following it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| aa7f35c | Michal Simek | 27 March 2018, 08:52:40 UTC | arm64: zynqmp: Use maxim prefix for all maxim chips Use vendor prefix for Maxim chips. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| b9d812b | Michal Simek | 27 March 2018, 08:47:26 UTC | arm64: zynqmp: Remove u-boot commands from dts files U-Boot commands shouldn't be the part of kernel DTS files. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 3b1efe3 | Michal Simek | 27 March 2018, 08:39:53 UTC | arm64: zynqmp: Remove number from clock-generator node name There shouldn't be a number appended based on spec. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 91e8a92 | Michal Simek | 27 March 2018, 08:38:08 UTC | arm64: zynqmp: Use i2c-mux instead of i2cswitch instead Based on review from mainline i2c-mux is standard name for i2c switches. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 693ef5c | Michal Simek | 27 March 2018, 08:36:39 UTC | arm64: zynqmp: Sync up license with mainline kernel Mainline Linux kernel has adopted SPDX header license in a different format then was used before. This patch is syncing it up. Also update years in License text and remove Nathalie's email because it is no longer valid. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 705bac9 | Vishal Sagar | 19 March 2018, 13:19:37 UTC | dma: xilinx: Add interlaced support to Xilinx Framebuffer driver Adds support for reading or setting the field id of framebuffer written to memory or read back from memory in the Xilinx Framebuffer driver. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:22 UTC |
| 11024d3 | Vishal Sagar | 13 March 2018, 19:35:37 UTC | v4l: xilinx: sdirxss: Correct the v4l2_field to V4L2_FIELD_ALTERNATE Correct the field type to V4L2_FIELD_ALTERNATE instead of V4L2_FIELD_INTERLACED and halve the height in such cases. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:17 UTC |
| e49124c | Saurabh Sengar | 13 March 2018, 03:56:26 UTC | bindings: display: xlnx: Fixing device tree documentation Adding back dma-names. Signed-off-by: Saurabh Sengar <saurabhs@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:10 UTC |
| 08447a4 | Vishal Sagar | 13 March 2018, 04:47:59 UTC | arm64: zynqmp: config: Enable soft PL V4L drivers Enable the Demosaic, Gamma, VPSS CSC, VPSS Scaler and MIPI CSI2 Rx drivers in defconfig. Signed-off-by: Vishal Sagar <vsagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:05 UTC |
| 9f2b19a | Venkateshwar Rao G | 14 March 2018, 06:33:47 UTC | arm64: zynqmp: config: Enable soft IP DRM drivers This enables VPSS scaler and color space converter drivers in defconfig. Signed-off-by: Venkateshwar Rao G <vgannava@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:54:01 UTC |
| 3dae1d9 | Shubhrajyoti Datta | 08 March 2018, 05:31:11 UTC | fpga: region: Add reset support to the fpga region Many of the fpga regions have a reset that has to be asserted after the bit file programming. Add support for the same in case there is no reset phandle passed no action is taken so it is backward compatible. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 23 April 2018, 09:53:53 UTC |
| 15b23f7 | Hyun Kwon | 10 April 2018, 16:22:21 UTC | drm: xlnx: zynqmp: Disable a plane when the fb format changes The drm core doesn't explicitly disable a plane when format changes. So add a check in the plane update functions if the new framebuffer format has changed, and disable the plane for the format change. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Tested-by: Kuldeep Dave <kuldeepd@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 April 2018, 12:36:37 UTC |
| 5ba3273 | Michal Simek | 11 April 2018, 10:35:35 UTC | arm64: zynqmp: Add support for zc1275 revB This patch enables support zc1275 revB board. It has SD added compared to revA. The same configuration will work for RevC boards aswell. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 11 April 2018, 10:37:54 UTC |
