| 043f8a2 | Michal Simek | 12 May 2020, 04:26:23 UTC | xilinx: Disable strict devmem access control Intention of the common kernel is ease of use and "demonstration of capabilities". The intention of these defconfigs is not to deploy these configurations on any real product. With keeping this in mind the patch disable strict devmem access control which can be used by some user space applications. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 12 May 2020, 04:57:18 UTC |
| c0b33b8 | Vishal Sagar | 05 May 2020, 05:08:10 UTC | staging: xlnxsync: Fix the uapi header license Error: missing "WITH Linux-syscall-note" for SPDX-License-Identifier Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 06 May 2020, 10:48:13 UTC |
| e4005b4 | Venkateshwar Rao Gannavarapu | 04 May 2020, 17:49:50 UTC | staging: xlnx_tsmux: Fix the uapi header license fixes Error: missing "WITH Linux-syscall-note" for SPDX-License-Identifier Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Venkateshwar Rao Gannavarapu <venkateshwar.rao.gannavarapu@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 06 May 2020, 10:48:13 UTC |
| d5bd4dd | Hyun Kwon | 02 May 2020, 01:55:42 UTC | v4l: xilinx: events: Fix the uapi header license Error: missing "WITH Linux-syscall-note" for SPDX-License-Identifier Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> | 06 May 2020, 10:48:13 UTC |
| f2b559a | Hyun Kwon | 02 May 2020, 01:55:18 UTC | v4l: xilinx: hls: Fix the uapi header license Error: missing "WITH Linux-syscall-note" for SPDX-License-Identifier Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> | 06 May 2020, 10:48:13 UTC |
| d16f10a | Hyun Kwon | 02 May 2020, 01:54:16 UTC | v4l: xilinx: sdi: Fix the uapi header license Error: missing "WITH Linux-syscall-note" for SPDX-License-Identifier Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> | 06 May 2020, 10:48:13 UTC |
| 325ecf9 | Hyun Kwon | 02 May 2020, 01:52:09 UTC | v4l: xilinx: csi: Fix the uapi header license Error: missing "WITH Linux-syscall-note" for SPDX-License-Identifier Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> | 06 May 2020, 10:48:13 UTC |
| 530dffd | Rafał Hibner | 28 April 2020, 08:02:51 UTC | dma: zynqmp_dma: Initialize descriptor list after freeing during reset List elements are not formally removed from list therefore list head is not initialized during zynqmp_dma_reset. This BUG causes kernel panic when transaction is unsuccessful: ------------[ cut here ]------------ [ 62.710730] list_add corruption. prev->next should be next (ffffffc07d308040), but was dead000000000100. (prev=ffffffc0540b40b8). [ 62.727960] WARNING: CPU: 0 PID: 1845 at /home/rafalh11/zynq_proj/zynq_platform/KERNEL/linux-xlnx/lib/list_debug.c:28 __list_add_valid+0x74/0xa0 [ 62.746374] Modules linked in: secom_mx_rpmsg(O) rpmsg_char secom_mx_retune(O) ad9680(O) ad5686_spi(O) ad5686(O) ad7298(O) ltc5594(O) lmx2594(O) ad8366(O) secom_mx(O) axi_jesd204_rx(O) axi_adxcvr(O) xilinx_transceiver(O) cf_axi_adc_core(O) hmc7044(O) [ 62.768546] CPU: 0 PID: 1845 Comm: mx Tainted: G O 4.19.0 #10 [ 62.775582] Hardware name: xlnx,zynqmp (DT) [ 62.779750] pstate: 60000005 (nZCv daif -PAN -UAO) [ 62.784524] pc : __list_add_valid+0x74/0xa0 [ 62.788690] lr : __list_add_valid+0x74/0xa0 [ 62.792855] sp : ffffff8008003da0 [ 62.796154] x29: ffffff8008003da0 x28: 0000000000000020 [ 62.801457] x27: 0000000000000000 x26: dead000000000100 [ 62.806760] x25: ffffffc07d308040 x24: ffffffc0540b40a0 [ 62.812064] x23: ffffffc07d308018 x22: 0000000000000000 [ 62.817359] x21: ffffffc07d308018 x20: ffffffc0540b40b8 [ 62.822654] x19: ffffffc0540b40b8 x18: ffffffffffffffff [ 62.827957] x17: 0000000000000000 x16: 0000000000000000 [ 62.833252] x15: ffffff8008f88648 x14: 3034303830336437 [ 62.838546] x13: ffffff8008f88670 x12: ffffff80085d0ec0 [ 62.843841] x11: ffffff8008f65018 x10: 0000000000000006 [ 62.849136] x9 : 657270202e6e6f69 x8 : 3462303435306366 [ 62.854431] x7 : 66666666663d7665 x6 : 00000000000001a2 [ 62.859726] x5 : 0000000000000064 x4 : 0000000000000000 [ 62.865020] x3 : 0000000000000000 x2 : ffffffffffffffff [ 62.870315] x1 : 0cbee765ba0ec900 x0 : 0000000000000000 [ 62.875611] Call trace: [ 62.878042] __list_add_valid+0x74/0xa0 [ 62.881864] zynqmp_dma_free_descriptor+0x48/0x100 [ 62.886644] zynqmp_dma_chan_desc_cleanup+0xb4/0xf8 [ 62.891505] zynqmp_dma_do_tasklet+0x68/0x110 [ 62.895847] tasklet_action_common.isra.3+0x7c/0x168 [ 62.900801] tasklet_action+0x24/0x30 [ 62.904447] __do_softirq+0x10c/0x200 [ 62.908092] irq_exit+0xac/0xc0 [ 62.911219] __handle_domain_irq+0x60/0xb0 [ 62.915305] gic_handle_irq+0x64/0xc0 [ 62.918951] el1_irq+0xb0/0x140 [ 62.922078] schedule_timeout+0x218/0x3a0 [ 62.926077] wait_for_common+0x170/0x268 [ 62.929983] wait_for_completion_timeout+0x10/0x18 [ 62.934761] ioctl+0x64/0x270 [secom_mx_retune] [ 62.939281] do_vfs_ioctl+0xb8/0x900 [ 62.942838] ksys_ioctl+0x44/0x90 [ 62.946137] __arm64_sys_ioctl+0x1c/0x28 [ 62.950044] el0_svc_common+0x60/0xe8 [ 62.953689] el0_svc_handler+0x6c/0x88 [ 62.957421] el0_svc+0x8/0xc [ 62.960284] ---[ end trace 91b4fdfe685446c4 ]--- [ 62.964934] ------------[ cut here ]------------ Signed-off-by: Rafal Hibner <rafal.hibner@secom.com.pl> Reviewed-by: Harini Katakam <harini.katakam@xilinx.com> Link: https://lore.kernel.org/linux-arm-kernel/20200428143225.3357-1-rafal.hibner@secom.com.pl/ State: waiting | 30 April 2020, 08:20:23 UTC |
| d3eb15a | Mubin Usman Sayyed | 28 April 2020, 13:59:43 UTC | xilinx: versal: Enable Xilinx soft interrupt controller Enabling Xilinx soft interrupt controller to serve PL interrupts routed through it. Signed-off-by: Mubin Usman Sayyed <mubin.usman.sayyed@xilinx.com> | 30 April 2020, 08:20:23 UTC |
| 591b80e | Shubhrajyoti Datta | 29 April 2020, 14:11:35 UTC | tty: xilinx_uartps: Add the id to the console Update the console index. Once the serial node is found update it to the console index. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/linux-arm-kernel/06195dc0effe2fb82e264e4faefcfdd6ebc00516.1588234277.git.michal.simek@xilinx.com/ State: waiting | 30 April 2020, 08:20:23 UTC |
| 6097416 | Raviteja Narayanam | 22 April 2020, 07:23:22 UTC | Revert "i2c: cadence: Fix the hold bit setting" This reverts commit d358def706880defa4c9e87381c5bf086a97d5f9. There are two issues with "i2c: cadence: Fix the hold bit setting" commit. 1. In case of combined message request from user space, when the HOLD bit is cleared in cdns_i2c_mrecv function, a STOP condition is sent on the bus even before the last message is started. This is because when the HOLD bit is cleared, the FIFOS are empty and there is no pending transfer. The STOP condition should occur only after the last message is completed. 2. The code added by the commit is redundant. Driver is handling the setting/clearing of HOLD bit in right way before the commit. The setting of HOLD bit based on 'bus_hold_flag' is taken care in cdns_i2c_master_xfer function even before cdns_i2c_msend/cdns_i2c_recv functions. The clearing of HOLD bit is taken care at the end of cdns_i2c_msend and cdns_i2c_recv functions based on bus_hold_flag and byte count. Since clearing of HOLD bit is done after the slave address is written to the register (writing to address register triggers the message transfer), it is ensured that STOP condition occurs at the right time after completion of the pending transfer (last message). Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> | 22 April 2020, 13:13:13 UTC |
| aa49d46 | Michal Simek | 30 March 2020, 09:35:38 UTC | arm64: zynqmp: Fix irps5401 device nodes - Do not use irps54012 as device node which is not correct. - Fix addresses of irps5401/u180 on zcu104 revisions. - Remove clock-cells property. It is PMIC without any clock output. - Define irps5401 nodes in zynqmp-e-a2197 Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 17 April 2020, 13:19:19 UTC |
| 21cbf7f | Michal Simek | 16 April 2020, 11:07:09 UTC | dt-bindings: spi: xilinx: Remove xlnx,num-ss-bits property This property has been removed by commit 102e6291f8b0 ("spi: xilinx: Update devicetree bindings for spi-xilinx") already but get back by merge commit 8a0be21c42a2 ("Merge remote-tracking branch 'xlnx_rebase_v5.4' into master-next-test") that's why remove it separately. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 16 April 2020, 11:26:22 UTC |
| 81566a0 | Raviteja Narayanam | 09 April 2020, 06:26:03 UTC | serial: uartps: Use cdns_uart_tx_empty in console_write Instead of accessing the registers and checking for tx_empty, use cdns_uart_tx_empty in cdns_uart_console_write function. Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> | 13 April 2020, 10:32:27 UTC |
| 5ceaf5a | Raviteja Narayanam | 09 April 2020, 06:26:02 UTC | serial: uartps: Wait for tx_empty in console setup On some platforms, the log is corrupted while console is being registered. It is observed that when set_termios is called, there are still some bytes in the FIFO to be transmitted. So, wait for tx_empty inside cdns_uart_console_setup before calling set_termios. Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> Reviewed-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> | 13 April 2020, 10:32:27 UTC |
| 69f773e | Jianqiang Chen | 10 April 2020, 16:51:04 UTC | drm: xlnx: pl_disp: make the incoming interlaced fields in order For interlace mode, the display driver expects the first field to be bottom field, and the frame buffer reader transfers the first field twice. In addition, the application may pass dummy packets before the video data. This patch guarantees the incoming field id to be flipped and drops any consecutive field. Signed-off-by: Jianqiang Chen <jianqiang.chen@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 13 April 2020, 06:35:55 UTC |
| e74af74 | Michal Simek | 10 April 2020, 11:45:14 UTC | gpio: xilinx: Change irq allocation from 0 location gpiod_to_irq() works with 0 as NO_IRQ. /* Zero means NO_IRQ */ if (!retirq) return -ENXIO; That's why use this temporary solution to start to allocation IRQs number for gpio controller with single line from 1 instead of 0 which is considered as NO_IRQ and value 0 is ignored even it is valid. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 10 April 2020, 11:59:02 UTC |
| 9edb0de | Naga Sureshkumar Relli | 10 April 2020, 04:50:26 UTC | mtd: spi-nor: Fix page size calculation Do not shift the page, as we are not updating this when we start supporting the ubifs. there are corner cases in ubifs where the page size can be unaligned, in this case the page size is wrongly calculated, which is causing failures in ubi stress test. where as in normal mtd tests and flashcp we will never see unaligned page sizes. Signed-off-by: Naga Sureshkumar Relli <naga.sureshkumar.relli@xilinx.com> | 10 April 2020, 08:17:13 UTC |
| 27e21ab | Piyush Mehta | 09 April 2020, 18:16:20 UTC | usb: dwc3: Enable clock when USB resume occurs USB clocks (which were disabled during suspend) need to be enabled during the resume. This patch does the same. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> | 10 April 2020, 08:17:13 UTC |
| 9ec825c | Rajan Vaja | 07 April 2020, 09:13:49 UTC | clk: fixed-factor: Don't register fixed factor clk until parent clk is registered "ecbf3f1795fd (clk: fixed-factor: Let clk framework find parent)" commit registers fixed factor clock even if parent clock is not registered. So when consumer tries to use fixed factor clock, it's parent may not have registered, which may create issue while getting parent rate and that will result in 0 clock rate for that fixed factor clock. To fix this, do not register fixed factor clock until parent clock is registered. Signed-off-by: Rajan Vaja <rajan.vaja@xilinx.com> State: not-upstreamable | 09 April 2020, 10:54:54 UTC |
| 3797bcd | Michal Simek | 09 April 2020, 10:46:34 UTC | xilinx: Enable module unloading Enable this feature. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 09 April 2020, 10:50:04 UTC |
| f1fd97d | Ben Levinsky | 06 April 2020, 14:20:07 UTC | remoteproc: zynq: Add explicit nodes for vrings This patch changes zynq driver to specify the firmware memory that is required explicitly. Without this, the driver will not work, as the CMA allocated memory will instead be used. In conjunction this patch also enables user to specify the vring and shared buffer location to ensure that only this aforementioned memory space is used. Signed-off-by: Ben Levinsky <ben.levinsky@xilinx.com> Acked-by: Wendy Liang <wendy.liang@xilinx.com> State: not-upstreamable | 07 April 2020, 12:36:14 UTC |
| 3d11061 | Piyush Mehta | 03 April 2020, 13:11:52 UTC | usb: dwc3: otg: remove otg static export warning This patch removes the static export warning, when USB OTG feature enables. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> | 06 April 2020, 14:09:24 UTC |
| 87d0c42 | Piyush Mehta | 03 April 2020, 13:11:51 UTC | usb: dwc3: otg: fix the function call used to get otg descriptor This patchs add missing size input arguments used in __usb_get_extra_descriptor,related to OTG get descriptor. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> | 06 April 2020, 14:09:23 UTC |
| 4cb67d7 | Nava kishore Manne | 06 April 2020, 13:22:49 UTC | fpga: versal: Use 32-bit DMA addressing PLM firmware uses PMC DMA to load/process the PDI image. The PMC DMA currently supporting only 32-bit operation.So This patch changes the 44 bit DMA mask to 32 bit. Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com> | 06 April 2020, 14:09:23 UTC |
| 3c41c3e | Michal Simek | 03 April 2020, 09:57:06 UTC | serial: uartps: Revert dynamic port allocation Based on several mainline discussions about dynamic port allocation recommendation is to revert the code which does it. The similar code is used on uartlite which has been reverted already in mainline. Here is the thread about it. https://lkml.kernel.org/r/cover.1585905873.git.michal.simek@xilinx.com Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 03 April 2020, 12:00:53 UTC |
| b33f9c8 | Ravi Shankar Jonnalagadda | 03 April 2020, 08:09:43 UTC | PCI: ZYNQMP EP driver: Adding Root DMA support PS PCIe DMA can be configured to be both End Point or Root DMA This patch adds support for Root DMA. Signed-off-by: Ravi Shankar Jonnalagadda <venkata.ravi.jonnalagadda@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> | 03 April 2020, 08:12:57 UTC |
| 9ce4644 | Bharat Kumar Gogada | 03 April 2020, 08:09:42 UTC | Revert "PCI: ZYNQMP EP driver: Adding Root DMA support" This reverts commit 3ea503f6179d29166512b4aa671688a867678e5c. The patch is broken when merging from kernel v4.19 to v5.4, some code part is missing compared to kernel v4.19, so reverting it. Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> | 03 April 2020, 08:12:56 UTC |
| 439d9ea | Michal Simek | 03 April 2020, 07:26:16 UTC | ARM: zynq: Enable TCP syncookie support for Zynq Enable this option which should be enabled by default these days. It's considered a basic Denial of Service mitigation. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 03 April 2020, 07:34:03 UTC |
| 66703c6 | Amit Kumar Mahapatra | 01 April 2020, 18:37:03 UTC | spi: spi-zynqmp-gqspi: Update driver to write appropriate dummy cycles as per the tx_buswidth The driver was not considering the tx_buswidth while updating the GenFifo with number of dummy cycles. This works fine when the tx_buswidth = 1 but when tx_buswidth = 4 the driver updates GenFifo with invalid number of dummy cycles. This results in data corruption. This patch fixes the issue and computes the right number of dummy cycles by taking into account tx_buswidth while calculating the number of dummy cycles. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> | 02 April 2020, 10:25:53 UTC |
| baa712a | Amit Kumar Mahapatra | 01 April 2020, 18:37:02 UTC | spi: spi-mem: Modify update_stripe api to handle different commands with same opcode value Write status register 2 command(SPINOR_OP_WRSR2) and 4byte Quad page program command(SPINOR_OP_PP_1_4_4_4B) has the same opcode(0x3e) value. In dual parallel mode the stripe flag of the transfer structure should be enabled for SPINOR_OP_PP_1_4_4_4B and disabled for SPINOR_OP_WRSR2 commands respectively. As per the current implementation of the update_stripe() api the stripe flag is disabled for both the commands. This patch modifies update_stripe() api to enable the stripe for SPINOR_OP_PP_1_4_4_4B and disable it for SPINOR_OP_WRSR2 commands. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> | 02 April 2020, 10:25:53 UTC |
| 9d6f04f | Florian Klink | 29 March 2020, 01:57:41 UTC | v4l: xilinx: multi-scaler: fix a printk format specifier Use %pa as printk format specifier for res->start, which is a resource_size_t, which is basically a phys_addr_t, and pass it by reference(documented in Documentation/core-api/printk-formats.rst). ``` drivers/media/platform/xilinx/xilinx-multi-scaler.c:2174:15: warning: format '%llx' expects argument of type 'long long unsigned int', but argument 4 has type 'resource_size_t' {aka 'unsigned int'} [-Wformat=] 2174 | dev_dbg(dev, "IO Mem 0x%llx mapped at %p\n", res->start, xm2msc->regs); | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ``` Signed-off-by: Florian Klink <flokli@flokli.de> Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> | 02 April 2020, 07:13:10 UTC |
| 6a8c6b2 | Ronak Shah | 30 March 2020, 15:39:43 UTC | ASoC: xlnx: Fixed I2S sound card registration issue Fixed mapping issue between I2S machine/card driver and I2S CPU driver for successful I2S sound card registration Signed-off-by: Ronak Shah <ronak.shah@xilinx.com> Tested-by: Daksha Rohit <dakshar@xilinx.com> Reviewed-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 02 April 2020, 07:13:10 UTC |
| ef412ed | Ben Levinsky | 31 March 2020, 17:58:30 UTC | remoteproc: zynqmp_r5: Add explicit nodes for vrings Match upstream remoteproc kernel driver convention and add device tree nodes for vrings. Do this explicitly to ensure appropriate ranges of memory are used for remoteproc communication. This patch accompanies linux patch to parse vrings such that if these nodes are present, then only use memory described with these nodes and not from CMA memory. Signed-off-by: Ben Levinsky <ben.levinsky@xilinx.com> Acked-by: Wendy Liang <wendy.liang@xilinx.com> State: not-upstreamable | 01 April 2020, 14:09:07 UTC |
| 67744a7 | Shubhrajyoti Datta | 01 April 2020, 09:30:00 UTC | dt-bindings: Fix the apm binding warnings Fix the binding warnings. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> | 01 April 2020, 14:09:07 UTC |
| a7f1c7d | Shubhrajyoti Datta | 31 March 2020, 12:12:15 UTC | clocking-wizard: Add versal clocking wizard support Add versal clocking wizard support Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> | 01 April 2020, 11:39:18 UTC |
| 2525fa2 | Shubhrajyoti Datta | 31 March 2020, 12:12:14 UTC | dt-bindings: Add versal clocking wizard Add versal clocking wizard support. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> | 01 April 2020, 11:39:18 UTC |
| 4756c39 | Raviteja Narayanam | 31 March 2020, 04:50:17 UTC | serial: uartps: Add TACTIVE check in cdns_uart_tx_empty function Make sure that all bytes are transmitted out of Uart by monitoring CDNS_UART_SR_TACTIVE bit as well. Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> Link: https://lore.kernel.org/r/e2514818af5973be291cc117d07739f068b71639.1584610774.git.shubhrajyoti.datta@xilinx.com State: upstream (706bbc572d5955272d4b67782a22083f8a6ad16a) Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> | 01 April 2020, 11:39:18 UTC |
| 153a363 | Raviteja Narayanam | 31 March 2020, 04:50:16 UTC | serial: uartps: Remove unconditional wait inside set_termios set_termios function should not wait for the transmit FIFO empty (CDNS_UART_SR_TXEMPTY) unconditionally. The tty layer takes care of it based on the parameter passed (TCSANOW/TCSADRAIN/TCSAFLUSH). Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> Link: https://lore.kernel.org/r/536e190dd5bbb474007a67e6323c048288942a28.1584610774.git.shubhrajyoti.datta@xilinx.com State: upstream (97451855cc3bb9ab0c222a44a66f068278ff6ccb) Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> | 01 April 2020, 11:39:18 UTC |
| bc1d49b | Hyun Kwon | 31 March 2020, 00:29:57 UTC | staging: apf: Make the APF config as a boolean state The xlnx.c uses low level functions such as __dma_map_area, that are not exposed symbols. So it can't build as a separate kernel module, but should be built as a kernel. So make the config as a boolean. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Reported-by: Florian Klink <flokli@flokli.de> | 31 March 2020, 11:11:26 UTC |
| 38bfe85 | Hyun Kwon | 31 March 2020, 00:29:56 UTC | misc: xilinx_flex: Fix the lock definitions First, it's defined as 'mutex' in struct while used by 'lock'. The build failed because of name mismatch. drivers/misc/xilinx_flex_pm.c:601:20: error: 'struct xflex_dev_info' has no member named 'mutex' 601 | mutex_init(&flexpm->mutex); | ^~ Then the lock scope was not correct, as it was never locked but unlocked on exit. Based on description, hold the lock in the beginning of sysfs entry point, then unlock before return. While at it, add the description for 'mutex' in struct. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Reported-by: Florian Klink <flokli@flokli.de> Cc: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> | 31 March 2020, 11:11:26 UTC |
| a45c1e3 | Hyun Kwon | 31 March 2020, 00:29:55 UTC | phy: zynqmp: check the config correctly Correct the config check, otherwise the module build fails as below. CC [M] drivers/phy/phy-zynqmp.o drivers/phy/phy-zynqmp.c:309:5: error: redefinition of 'xpsgtr_override_deemph' 309 | int xpsgtr_override_deemph(struct phy *phy, u8 plvl, u8 vlvl) | ^~~~~~~~~~~~~~~~~~~~~~ In file included from drivers/phy/phy-zynqmp.c:24: ./include/linux/phy/phy-zynqmp.h:25:19: note: previous definition of 'xpsgtr_override_deemph' was here 25 | static inline int xpsgtr_override_deemph(struct phy *base, u8 plvl, u8 vlvl) | ^~~~~~~~~~~~~~~~~~~~~~ drivers/phy/phy-zynqmp.c:326:5: error: redefinition of 'xpsgtr_margining_factor' 326 | int xpsgtr_margining_factor(struct phy *phy, u8 plvl, u8 vlvl) | ^~~~~~~~~~~~~~~~~~~~~~~ In file included from drivers/phy/phy-zynqmp.c:24: ./include/linux/phy/phy-zynqmp.h:30:19: note: previous definition of 'xpsgtr_margining_factor' was here 30 | static inline int xpsgtr_margining_factor(struct phy *base, u8 plvl, u8 vlvl) | ^~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Cc: Anurag Kumar Vulisha <anurag.kumar.vulisha@xilinx.com> | 31 March 2020, 11:11:26 UTC |
| 9e6a559 | Florian Klink | 31 March 2020, 00:29:54 UTC | drm: xlnx: fix some typos in the Kconfig help texts Fix some typos in the Kconfig help texts. Signed-off-by: Florian Klink <flokli@flokli.de> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 31 March 2020, 11:11:26 UTC |
| 2b000a3 | Florian Klink | 31 March 2020, 00:29:53 UTC | drm/i2c: adv7511: add missing include to drm/drm_probe_helper.h Otherwise, the compiler complains about not being able to find the `drm_helper_hpd_irq_event` symbol: ``` drivers/gpu/drm/i2c/adv7511.c: In function 'adv7511_irq_process': drivers/gpu/drm/i2c/adv7511.c:450:3: error: implicit declaration of function 'drm_helper_hpd_irq_event' [-Werror=implicit-function-declaration] 450 | drm_helper_hpd_irq_event(adv7511->encoder->dev); | ^~~~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Florian Klink <flokli@flokli.de> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 31 March 2020, 11:11:26 UTC |
| c13b36a | Sai Krishna Potthuri | 30 March 2020, 16:20:08 UTC | mtd: cadence-quadspi: Fix the issues in Rx Periodic tuning Use complete_all() for tuning_complete and request_complete to avoid the timeout errors for mtd requests (read, write and erase) and periodic tuning requests respectively. This patch also taken care of acquiring request_complete lock before checking the tuning complete to avoid tuning timeout. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> | 31 March 2020, 11:11:25 UTC |
| aa3f6d4 | Michal Simek | 26 March 2020, 12:42:02 UTC | irqchip: xilinx: Change level for cpu-id warning Report missing cpu-id property only in debug mode. Only Microblaze SMP is using this property which is pretty much a rare case and doesn't make sense to disturb all bootlogs. Reported-by: Punnaiah Choudary Kalluri <punnaiah.choudary.kalluri@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 26 March 2020, 13:15:18 UTC |
| 4ad9899 | Michal Simek | 24 March 2020, 16:53:53 UTC | dt-bindings: versal: Add new PM_DEV_AI and PM_DEV_GPIO_PMC macros Extend header with new macros and also update years. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 25 March 2020, 07:46:47 UTC |
| 62a5007 | Piyush Mehta | 24 March 2020, 06:15:40 UTC | usb: dwc3: when enters in d3 state This patch adds wakeup_capable and is_d3 flag handling in suspend function, when host enters in d3 state and disable clock. Signed-off-by: Piyush Mehta <piyush.mehta@xilinx.com> | 24 March 2020, 12:17:59 UTC |
| 2fd4513 | Srinivas Neeli | 23 March 2020, 17:53:04 UTC | gpio: gpio-xilinx: use module_platform_driver to simplify the code module_platform_driver() makes the code simpler by eliminating boilerplate code. Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com> | 24 March 2020, 12:17:59 UTC |
| 008a7e4 | Srinivas Neeli | 23 March 2020, 17:53:03 UTC | gpio: zynq: use module_platform_driver to simplify the code module_platform_driver() makes the code simpler by eliminating boilerplate code. Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com> | 24 March 2020, 12:17:59 UTC |
| a1d2beb | Srinivas Neeli | 23 March 2020, 17:53:02 UTC | pinctrl: zynq: use module_platform_driver to simplify the code module_platform_driver() makes the code simpler by eliminating boilerplate code. Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com> | 24 March 2020, 12:17:58 UTC |
| 065cafc | Srinivas Neeli | 23 March 2020, 17:53:01 UTC | pinctrl: zynqmp: use module_platform_driver to simplify the code module_platform_driver() makes the code simpler by eliminating boilerplate code. Signed-off-by: Srinivas Neeli <srinivas.neeli@xilinx.com> | 24 March 2020, 12:17:58 UTC |
| 530c4c4 | Hyun Kwon | 23 March 2020, 16:58:29 UTC | drm: xlnx: bridge: make xlnx_bridge_set_timing() static inline Without inline, it gives below compile warning. drivers/gpu/drm/xlnx/xlnx_bridge.h:149:12: warning: ‘xlnx_bridge_set_timing’ defined but not used [-Wunused-function] static int xlnx_bridge_set_timing(struct xlnx_bridge *bridge, ^~~~~~~~~~~~~~~~~~~~~~ Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> | 24 March 2020, 12:17:58 UTC |
| 7ec1c3a | Amit Kumar Mahapatra | 22 March 2020, 11:09:53 UTC | mtd: spi-nor: Fix warnings Fixed the following warnings: drivers/mtd/spi-nor/spi-nor.c: In function ‘spi_nor_write_ear’: drivers/mtd/spi-nor/spi-nor.c:691:5: warning: variable ‘code’ set but not used [-Wunused-but-set-variable] u8 code; ^~~~ drivers/mtd/spi-nor/spi-nor.c: In function ‘spi_nor_read’: drivers/mtd/spi-nor/spi-nor.c:2898:9: warning: variable ‘addr’ set but not used [-Wunused-but-set-variable] loff_t addr = 0; ^~~~ drivers/mtd/spi-nor/spi-nor.c: In function ‘spi_nor_switch_micron_octal_ddr’: drivers/mtd/spi-nor/spi-nor.c:4917:5: warning: variable ‘program_opcode’ set but not used [-Wunused-but-set-variable] u8 program_opcode; ^~~~~~~~~~~~~~ drivers/mtd/spi-nor/spi-nor.c:779: warning: Function parameter or member 'info' not described in 'read_ear' drivers/mtd/spi-nor/spi-nor.c:701 spi_nor_write_ear() warn: right shifting more than type allows 8 vs 24 drivers/mtd/spi-nor/spi-nor.c:2921 spi_nor_read() warn: possible memory leak of 'ptr' drivers/mtd/spi-nor/spi-nor.c:721 spi_nor_write_ear() error: uninitialized symbol 'code'. drivers/mtd/spi-nor/spi-nor.c:728 spi_nor_write_ear() error: uninitialized symbol 'code'. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> | 23 March 2020, 10:33:20 UTC |
| ae8be0c | Sergei Korneichuk | 19 March 2020, 19:49:25 UTC | remoteproc: zynq: Fix license, code style Convert to SPDX license and fix style problems. Signed-off-by: Sergei Korneichuk <sergei.korneichuk@xilinx.com> | 23 March 2020, 10:32:37 UTC |
| 603c919 | Sergei Korneichuk | 19 March 2020, 19:49:24 UTC | remoteproc: zynq: Fix indentation Fix alignment and blank line checks. Signed-off-by: Sergei Korneichuk <sergei.korneichuk@xilinx.com> | 23 March 2020, 10:31:05 UTC |
| 04b3084 | Rob Herring | 02 March 2020, 17:36:20 UTC | dt-bindings: bus: Drop empty compatible string in example In preparation to add generic checks of compatible strings, drop the compatible as '...' is not a valid compatible string. Cc: Maxime Ripard <mripard@kernel.org> Cc: Chen-Yu Tsai <wens@csie.org> Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Rob Herring <robh@kernel.org> | 23 March 2020, 10:28:51 UTC |
| ca541f8 | Rob Herring | 17 December 2019, 16:27:12 UTC | dt-bindings: Add missing 'properties' keyword enclosing 'snps,tso' DT property definitions must be under a 'properties' keyword. This was missing for 'snps,tso' in an if/then clause. A meta-schema fix will catch future errors like this. Fixes: 7db3545aef5f ("dt-bindings: net: stmmac: Convert the binding to a schemas") Cc: "David S. Miller" <davem@davemloft.net> Acked-by: Maxime Ripard <mripard@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> | 23 March 2020, 10:24:08 UTC |
| 6e7c258 | Rob Herring | 21 November 2019, 23:06:47 UTC | dt-bindings: interrupt-controller: arm,gic-v3: Add missing type to interrupt-partition-* nodes Add missing 'type: object' schema to interrupt-partition-* nodes. Found with fix to meta-schema checks. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Acked-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Rob Herring <robh@kernel.org> | 23 March 2020, 10:24:07 UTC |
| e846690 | Rob Herring | 21 November 2019, 22:57:03 UTC | dt-bindings: firmware: ixp4xx: Drop redundant minItems/maxItems The minItems/maxItems default to the number of items in an 'items' list, so drop the redundant specifying of them here. Signed-off-by: Rob Herring <robh@kernel.org> | 23 March 2020, 10:24:07 UTC |
| c055e6c | Vishal Sagar | 20 March 2020, 11:36:03 UTC | clk: idt: Fix i2cwritebulk() failure Commit 8b9f9d4dc511 ("regmap: verify if register is writeable before writing operations") introduces new way for validating the writable register range. This causes the idt driver to fail as max_register is only 0xFF and reg address falls outside it. This works earlier as the writeable_reg() function pointer to idt24x_regmap_is_writeable() is used which always returns true. So to pass the validation, the max_register is now set to 0xFFFF. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| 21b6fe7 | Madhurkiran Harikrishnan | 20 March 2020, 00:16:03 UTC | xilinx: Do not compress kernel modules Disable CONFIG_MODULE_COMPRESS to sync with previous configs. To enable this, the userspace needs to align and be able to handle compressed modules properly. Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| fc05bdb | Hyun Kwon | 12 March 2020, 20:39:28 UTC | v4l: xilinx: vipp: Remove set streaming on subdev Now xvip_graph_entity is available on all calling sites. No need to get subdev from graph entity and iterate to get the graph entity back. Use the graph entity directly, and remove the loop. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Dylan Yip <dylan.yip@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| 98bfb37 | Hyun Kwon | 12 March 2020, 20:30:39 UTC | v4l: xilinx: vipp: Change xvip_entity_start/stop to take graph entity Direct use of xvip_graph_entity will allow translation from subdev back to graph entity. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Dylan Yip <dylan.yip@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| b0bbedc | Hyun Kwon | 12 March 2020, 17:31:38 UTC | v4l: xilinx: vipp: remove a loop for graph start / stop Let's try to set the dependency sub-devices recursively while checking. It allows to resolve dependencies in one shot, hence removing the repeated loop. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Dylan Yip <dylan.yip@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| 8602454 | Hyun Kwon | 12 March 2020, 17:17:58 UTC | v4l: xilinx: vipp: do enabling in the dependency check This patch moves the enabling/disabling as a part of dependency check. Since it's not just a dependency check anymore, rename the function. It removes the error return, so there can be false postive. Not fixing here in this commit because it'll be removed in following patch anyway. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Dylan Yip <dylan.yip@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| aa0df41 | Hyun Kwon | 11 March 2020, 22:34:03 UTC | v4l: xilinx: vipp: use async list for start and stop Check dependencies (sink or source) based on steam on / off, to sequence enabling / disabling sub-devices, using the asd list. The current implementation relies on the depth first media graph walk, which doesn't take the direction(sink / source) into account. When there's an entity with multiple source pads, it ends up enabling the sink first. So the list created from media graph walk becomes meaningless in terms of ordering, but just holds all subdevs in the graph. That is how asd list is used in xilinx-vipp already. And doing it for all dmas in the graph will just waste iterations for no benefit: all are set in first iteration, and all following iterations are null. This patch instead iterates the asd list and checkes the dependencies before enabling / disabling. This process is repeated until there's no change in sub-device enable/disable state, which means all sub-devices are handled or dependencies can't be met. Iterating through DMAs is removed because all sub-devices are captured in asd list anyway as explained. More efficient way than repeating iterations to resolve dependencies would be just to follow the link and perform in correct order. It can be solved on top of this. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Dylan Yip <dylan.yip@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| 39c4d29 | Hyun Kwon | 11 March 2020, 21:57:56 UTC | v4l: xilinx: vipp: move xvip_entity_start_stop() to xilinx-vipp This is a preparation to do the graph level stream on/off handling in xilinx-vipp. Rename an argument name to align: 'start' to 'on'. Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com> Reviewed-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Dylan Yip <dylan.yip@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| 388b5af | Vishal Sagar | 16 March 2020, 06:07:10 UTC | v4l: xilinx: xsdirxss: Fix format height for interlaced and pSF mode When the transport is interlaced for 1080 line streams whose picture type is progressive, the image format dimensions are 1920x540 instead of 1920x1080. In 3GB DL psF mode the video is similar to interlaced as even though the content is progressive, the transport is interlaced and is sent as two width x (height/2) buffers. In both cases, the field id will toggle like interlaced mode. So set the field type as V4L2_FIELD_ALTERNATE. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| 51f9886 | Vishal Sagar | 16 March 2020, 06:07:09 UTC | v4l: xilinx: sdirxss: Add support for ST2081-10 Mode 2 in 6G mode Add support for ST2081-10 Mode 2 which allows carriage of 1080 line source image formats and ancillary data in a single link 6G-SDI interface. These different image formats are RGB/YUV444/YUV422 10/12 bpc in 2048/1920x1080p60/59.97/50/48/47.95 in 6G mode. For details refer to ST2081-10:2018 Section 5 Table 6. https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=8320055 Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| e650346 | Vishal Sagar | 16 March 2020, 06:07:08 UTC | v4l: xilinx: sdirxss: Add new 10/12 bit support Add support for new 10 and 12 bit modes. The IP is configured to be in 10 or 12 bit mode in design. Even though the streams of 10 bit will be recognized by core in 12 bit configuration and vice versa, the data coming from the core will be corrupted. So a check is added in driver to loose video lock in case 10 bit stream in detected in 12 bit mode and vice versa. This patch now adds support for nearly 200 combinations of resolution, frame rate and color format in 3GA, 3GB, 6G and 12G modes. Based on IP configuration, either 4 10 bit or 4 12 bit media bus formats are enumerated. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| 604ee87 | Vishal Sagar | 16 March 2020, 06:07:07 UTC | dt: bindings: media: xilinx: sdirxss : Add bit depth optional property Add an optional property "xlnx,bpp" which denotes the bit depth configured in the IP core. The default value is 10. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| 5589054 | Vishal Sagar | 16 March 2020, 06:07:06 UTC | v4l: xilinx: sdirxss: Add support for optional gt reset gpio Add an optional device tree parameter to get gpio handle to reset the fmc init done pin in compact GT. This signal is active low. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| 177c760 | Vishal Sagar | 16 March 2020, 06:07:05 UTC | dt: bindings: media: xilinx: sdirxss : Add GT reset gpio handle Add optional property to reset the compact GT using a GPIO pin connected to fmc init done pin. This signal is active low. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| fc9552a | Vishal Sagar | 16 March 2020, 06:07:04 UTC | v4l: xilinx: sdirxss: Fix IP reset on gt clock switch in 12G mode On changing the GT clock from integer to fractional or vice versa, it is observed that the IP resets. So the core is unable to detect the incoming stream. The IP needs to be restored back to its state. So save the control values and use them to reconfgure the SDI Rx IP after the GT clock has changed. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 20 March 2020, 22:54:49 UTC |
| fc28b25 | Shubhrajyoti Datta | 18 March 2020, 18:08:02 UTC | clk: clock-wizard: Remove a unnessary type cast Remove a unnecessary type cast. Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com> | 19 March 2020, 06:28:59 UTC |
| 23d8af9 | Michal Simek | 19 March 2020, 06:19:08 UTC | xilinx: Disable SMMU for all arm64 configs In conjunction with commit 0c860084583c ("xilinx: versal: Disable SMMU for now") also disabling SMMU for all arm64 Xilinx configs. How to enable/use SMMU will be described through the Xilinx wiki. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 19 March 2020, 06:25:50 UTC |
| db63682 | Sergei Korneichuk | 18 March 2020, 04:32:55 UTC | remoteproc: zynq_remoteproc: remove unused variable Remove unused variable rsc to fix a warning in zynq_rproc_kick. Signed-off-by: Sergei Korneichuk <sergei.korneichuk@xilinx.com> | 18 March 2020, 13:08:29 UTC |
| 9e34692 | Raviteja Narayanam | 13 March 2020, 06:18:25 UTC | i2c: xiic: Fix Rx and Tx paths in standard mode repeated start When a combined message request comes from user space, the controller has to initiate repeated start sequence. In standard mode, this repeated start sequence is corrupted if there is still data in the Tx FIFO. So, always make sure that all the bytes are completely transmitted out of the FIFO by waiting for TXEMPTY, if the previous message is of Tx type. Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> | 18 March 2020, 13:08:29 UTC |
| 9c073de | Raviteja Narayanam | 13 March 2020, 06:18:03 UTC | i2c: xiic: Correct the datatype for rx_watermark The message length data type should be u16 as per the i2c_msg structure Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> | 18 March 2020, 13:08:29 UTC |
| 0eb57d3 | Tejas Patel | 12 March 2020, 14:40:47 UTC | clk: zynqmp: Fix CLK_FRAC bit index This patch fixes fdbb2e62f6a5 (clk: zynqmp: Update CLK_FRAC support as per upstream) CLK_FRAC is stored in BIT(4) of in TF-A type flags. While storing custom type flags in custom_type_flag variable it is already being shifted by 4. So in custom_type_flag variable bit index of CLK_FRAC flag would be 0 and not 4. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> | 18 March 2020, 13:08:29 UTC |
| 4169e7e | Dylan Yip | 10 March 2020, 17:37:12 UTC | v4l: xilinx: dma: Prevent divide by zero error Currently there is no issue, but there is a possibility of a divide by zero. This was found during a coverity check which gave the following error: "Event zero_return: Function call "lcm(dma->align, info->bpp >> 3)" returns 0." This patch fixes this by adding a check to see if the calculated divisor is 0. Signed-off-by: Dylan Yip <dylan.yip@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 18 March 2020, 13:08:29 UTC |
| 9eabf2f | Vishal Sagar | 17 March 2020, 11:56:19 UTC | v4l: xilinx: xcsi2rxss: Move DPHY offset to 4K instead of 64K The DPHY offset has been moved to 4K from 64K to reduce the address space used by the MIPI CSI2 Rx subsystem when DPHY register interface is enabled. For this a new compatible string v5_0 is added. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 18 March 2020, 13:08:29 UTC |
| 6e87ab2 | Vishal Sagar | 17 March 2020, 11:56:18 UTC | dt-bindings: media: xilinx: csi2rxss: Add 5.0 compatible string The DPHY Rx base address offset is moved from 0x1_0000(64K) to 0x1000 (4K) to reduce the address space used by the subsystem. For this new compatible string v5_0 is added. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 18 March 2020, 13:08:29 UTC |
| a8df1a9 | Vishal Sagar | 07 March 2020, 06:12:27 UTC | v4l: xilinx: sdirxss: Fix returning error on stream off When yavta app is started and the cable removed, a video unlock event occurs. In this context the streaming is stopped as the bridges are disabled. Now killing the yavta application calls s_stream() with enable as false which returns -EINVAL. So when yavta is restarted after cable is connected and video is locked, the V4L framework doesn't call s_stream() with enable = true as it still believes that SDI Rx subdev is still streaming. This is fixed by returning success for s_stream() with enable = false even when streaming is disabled. Signed-off-by: Vishal Sagar <vishal.sagar@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 18 March 2020, 13:08:29 UTC |
| e436544 | Swagath Gadde | 15 March 2020, 06:20:38 UTC | xilinx: zynq: Enable soft interrupt controller for PL interrupts This patch enables axi based soft interrupt controller to be able to handle more interrupts coming from PL. Signed-off-by: Swagath Gadde <swagath.gadde@xilinx.com> | 18 March 2020, 13:08:28 UTC |
| 92ae042 | Swagath Gadde | 14 March 2020, 10:51:35 UTC | xilinx: zynq: Enable drm for zynq This patch enables the drm in zynq defconfig which is required for zocl. Signed-off-by: Swagath Gadde <swagath.gadde@xilinx.com> | 18 March 2020, 13:08:28 UTC |
| 7fd1899 | Dylan Yip | 10 March 2020, 23:49:27 UTC | arm64: zynqmp: Enable CONFIG_MEMORY_HOTPLUG in defconfig Due to changes in v5.4 kernel, Xilinx out-of-tree VCU modules now utilizes a PL reserved memory pool which is registered into memory sections using the Memory Hotplug API. To use this API, we must enable CONFIG_MEMORY_HOTPLUG. Signed-off-by: Dylan Yip <dylan.yip@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 18 March 2020, 13:08:28 UTC |
| 6d1ffa8 | Michal Simek | 09 March 2020, 14:06:00 UTC | dma: xilinx: Replace dma_zalloc_coherent API with dma_alloc_coherent This patch replaces "dma_zalloc_coherent" API with "dma_alloc_coherent" as it was deprecated in 5.4 kernel by commit 750afb08ca71 ("cross-tree: phase out dma_zalloc_coherent()"). Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 09 March 2020, 14:07:15 UTC |
| 42b63c6 | Venkateshwar Rao Gannavarapu | 09 March 2020, 09:57:54 UTC | staging: xlnx_tsmux: replace dma_zalloc_coherent API with dma_alloc_coherent This patch replaces "dma_zalloc_coherent" API with "dma_alloc_coherent" as it was deprecated in 5.4 kernel by commit 750afb08ca71 ("cross-tree: phase out dma_zalloc_coherent()") Signed-off-by: Venkateshwar Rao Gannavarapu <venkateshwar.rao.gannavarapu@xilinx.com> | 09 March 2020, 14:07:15 UTC |
| e1633c5 | Raviteja Narayanam | 05 March 2020, 17:40:02 UTC | i2c: xiic: Enter standard mode only for > 255 byte read transfers When standard mode is used for all the read transfers, timing of interrupts is not in sync with the hardware. So, to avoid breaking existing scenarios, enter standard mode only when the size of read transfer is > 255 bytes. Signed-off-by: Raviteja Narayanam <raviteja.narayanam@xilinx.com> | 09 March 2020, 09:45:17 UTC |
| b4e9e0e | Rohit Visavalia | 06 March 2020, 14:40:13 UTC | sound: soc: xilinx: Use unique dai link per device Define and assign unique dai link for both dp audio devices and also add stream_name for device. Signed-off-by: Rohit Visavalia <rohit.visavalia@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 09 March 2020, 09:41:45 UTC |
| 149b142 | Venkateshwar Rao Gannavarapu | 06 March 2020, 08:49:11 UTC | drm: xlnx: mixer: Add support to update the color space conversion coefficients This patch adds the support to Mixer 5.0 with backward compatibility. It enables the COLOR_ENCODING and COLOR_RANGE properties to support BT601/709/2020 color encoding schemes with limited and full range. Signed-off-by: Venkateshwar Rao Gannavarapu <venkateshwar.rao.gannavarapu@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 09 March 2020, 09:41:45 UTC |
| fd076a5 | Venkateshwar Rao Gannavarapu | 06 March 2020, 08:49:10 UTC | dt-bindings: display: xlnx: mixer: Add rev 5.0 to compatible string This patch updates the compatible string and colorimetry coefficient entry to support 5.0 IP version. The mixer 5.0 IP introduces config registers to program the coefficients for color space conversion. Signed-off-by: Venkateshwar Rao Gannavarapu <venkateshwar.rao.gannavarapu@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 09 March 2020, 09:41:45 UTC |
| 33f8d94 | Madhurkiran Harikrishnan | 03 March 2020, 23:14:44 UTC | drm/fb_helper: Enable drm_leak_fbdev_smem by default for zynqmp As Mali400 user-space implementation relies on the physical address to render into framebufffer and lot of use-case depends on this backend, enable the module parameter 'drm_leak_fbdev_smem' by default. The feature is deprecated in upstream due to the security concern, but no alternative solution is given. For more information, refer to kernel commit 4be9bd10e22d ("drm/fb_helper: Allow leaking fbdev smem_start"). This patch is Xilinx specific and not upstreamable. Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 09 March 2020, 09:41:45 UTC |
| 5dc56e6 | Madhurkiran Harikrishnan | 03 March 2020, 23:14:43 UTC | xilinx: zynqmp: Enable CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM in defconfig Enabling CONFIG_DRM_FBDEV_LEAK_PHYS_SMEM gives the user a choice whether or not to share the physical addrees of the frame buffer to user-space via FBIOGET_FSCREENINFO ioctl. As Mali400 user-space implementation relies on the physical address of the framebuffer for rendering. The feature is deprecated in upstream due to the security concern, but no alternative solution is given. For more information, refer to kernel commit 4be9bd10e22d ("drm/fb_helper: Allow leaking fbdev smem_start"). This patch is Xilinx specific and not upstreamable. Signed-off-by: Madhurkiran Harikrishnan <madhurkiran.harikrishnan@xilinx.com> Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com> | 09 March 2020, 09:37:02 UTC |
| f020e7d | Tejas Prajapati Rameshchandra | 03 March 2020, 13:35:25 UTC | mtd: spi-nor: Flash devices with quad mode support added. block protected lock and unlock support added. Quad mode has to be enabled for spansion flash part writing into the Config Register. Signed-off-by: Amit Kumar Mahapatra <amit.kumar-mahapatra@xilinx.com> Signed-off-by: Tejas Prajapati Rameshchandra <tejaspra@xilinx.com> | 05 March 2020, 06:59:34 UTC |
| 4914ff0 | Sai Krishna Potthuri | 03 March 2020, 11:38:34 UTC | mtd: cadence-quadspi: Fixed compilation warnings This patch fixes following compilation warnings. 1. warning: variable ddata set but not used [-Wunused-but-set-variable]. 2. line 2179 is redundant because platform_get_irq() already prints an error. 3. warning: unused variable ‘dev’ [-Wunused-variable]. 4. warning: unused variable ‘pdev’ [-Wunused-variable]. Signed-off-by: Sai Krishna Potthuri <lakshmi.sai.krishna.potthuri@xilinx.com> State: pending | 05 March 2020, 06:59:33 UTC |
| c816b76 | Michal Simek | 06 February 2020, 12:09:32 UTC | xilinx: Create single kernel image to support ZynqMP/Versal This single config is used for kernel configuration which should work on ZynqMP and Versal Xilinx SoCs. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 04 March 2020, 14:57:50 UTC |
| 0c86008 | Michal Simek | 04 March 2020, 14:56:18 UTC | xilinx: versal: Disable SMMU for now HW designs with SMMU on should be validated by hand one by one that's why disable this default option for now. When all devices are validated we can enable it again. Signed-off-by: Michal Simek <michal.simek@xilinx.com> | 04 March 2020, 14:57:25 UTC |
