Revision 0251d196b0e1a19c870be882e5d4f496de8ab758 authored by Guangbin Huang on 27 October 2021, 12:11:45 UTC, committed by David S. Miller on 27 October 2021, 13:47:33 UTC
Currently, if there is a reset event triggered by RAS during device in initialization process, driver may run reset process concurrently with initialization process. In this case, it may cause problem. For example, the RSS indirection table may has not been alloc memory in initialization process yet, but it is used in reset process, it will cause a call trace like this: [61228.744836] Unable to handle kernel NULL pointer dereference at virtual address 0000000000000000 ... [61228.897677] Workqueue: hclgevf hclgevf_service_task [hclgevf] [61228.911390] pstate: 40400009 (nZcv daif +PAN -UAO -TCO BTYPE=--) [61228.918670] pc : hclgevf_set_rss_indir_table+0xb4/0x190 [hclgevf] [61228.927812] lr : hclgevf_set_rss_indir_table+0x90/0x190 [hclgevf] [61228.937248] sp : ffff8000162ebb50 [61228.941087] x29: ffff8000162ebb50 x28: ffffb77add72dbc0 x27: ffff0820c7dc8080 [61228.949516] x26: 0000000000000000 x25: ffff0820ad4fc880 x24: ffff0820c7dc8080 [61228.958220] x23: ffff0820c7dc8090 x22: 00000000ffffffff x21: 0000000000000040 [61228.966360] x20: ffffb77add72b9c0 x19: 0000000000000000 x18: 0000000000000030 [61228.974646] x17: 0000000000000000 x16: ffffb77ae713feb0 x15: ffff0820ad4fcce8 [61228.982808] x14: ffffffffffffffff x13: ffff8000962eb7f7 x12: 00003834ec70c960 [61228.991990] x11: 00e0fafa8c206982 x10: 9670facc78a8f9a8 x9 : ffffb77add717530 [61229.001123] x8 : ffff0820ad4fd6b8 x7 : 0000000000000000 x6 : 0000000000000011 [61229.010249] x5 : 00000000000cb1b0 x4 : 0000000000002adb x3 : 0000000000000049 [61229.018662] x2 : ffff8000162ebbb8 x1 : 0000000000000000 x0 : 0000000000000480 [61229.027002] Call trace: [61229.030177] hclgevf_set_rss_indir_table+0xb4/0x190 [hclgevf] [61229.039009] hclgevf_rss_init_hw+0x128/0x1b4 [hclgevf] [61229.046809] hclgevf_reset_rebuild+0x17c/0x69c [hclgevf] [61229.053862] hclgevf_reset_service_task+0x4cc/0xa80 [hclgevf] [61229.061306] hclgevf_service_task+0x6c/0x630 [hclgevf] [61229.068491] process_one_work+0x1dc/0x48c [61229.074121] worker_thread+0x15c/0x464 [61229.078562] kthread+0x168/0x16c [61229.082873] ret_from_fork+0x10/0x18 [61229.088221] Code: 7900e7f6 f904a683 d503201f 9101a3e2 (38616b43) [61229.095357] ---[ end trace 153661a538f6768c ]--- To fix this problem, don't schedule reset task before initialization process is done. Signed-off-by: Guangbin Huang <huangguangbin2@huawei.com> Signed-off-by: David S. Miller <davem@davemloft.net>
1 parent f29da40
u8500_hsem.c
// SPDX-License-Identifier: GPL-2.0
/*
* u8500 HWSEM driver
*
* Copyright (C) 2010-2011 ST-Ericsson
*
* Implements u8500 semaphore handling for protocol 1, no interrupts.
*
* Author: Mathieu Poirier <mathieu.poirier@linaro.org>
* Heavily borrowed from the work of :
* Simon Que <sque@ti.com>
* Hari Kanigeri <h-kanigeri2@ti.com>
* Ohad Ben-Cohen <ohad@wizery.com>
*/
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/io.h>
#include <linux/slab.h>
#include <linux/spinlock.h>
#include <linux/hwspinlock.h>
#include <linux/platform_device.h>
#include "hwspinlock_internal.h"
/*
* Implementation of STE's HSem protocol 1 without interrutps.
* The only masterID we allow is '0x01' to force people to use
* HSems for synchronisation between processors rather than processes
* on the ARM core.
*/
#define U8500_MAX_SEMAPHORE 32 /* a total of 32 semaphore */
#define RESET_SEMAPHORE (0) /* free */
/*
* CPU ID for master running u8500 kernel.
* Hswpinlocks should only be used to synchonise operations
* between the Cortex A9 core and the other CPUs. Hence
* forcing the masterID to a preset value.
*/
#define HSEM_MASTER_ID 0x01
#define HSEM_REGISTER_OFFSET 0x08
#define HSEM_CTRL_REG 0x00
#define HSEM_ICRALL 0x90
#define HSEM_PROTOCOL_1 0x01
static int u8500_hsem_trylock(struct hwspinlock *lock)
{
void __iomem *lock_addr = lock->priv;
writel(HSEM_MASTER_ID, lock_addr);
/* get only first 4 bit and compare to masterID.
* if equal, we have the semaphore, otherwise
* someone else has it.
*/
return (HSEM_MASTER_ID == (0x0F & readl(lock_addr)));
}
static void u8500_hsem_unlock(struct hwspinlock *lock)
{
void __iomem *lock_addr = lock->priv;
/* release the lock by writing 0 to it */
writel(RESET_SEMAPHORE, lock_addr);
}
/*
* u8500: what value is recommended here ?
*/
static void u8500_hsem_relax(struct hwspinlock *lock)
{
ndelay(50);
}
static const struct hwspinlock_ops u8500_hwspinlock_ops = {
.trylock = u8500_hsem_trylock,
.unlock = u8500_hsem_unlock,
.relax = u8500_hsem_relax,
};
static int u8500_hsem_probe(struct platform_device *pdev)
{
struct hwspinlock_pdata *pdata = pdev->dev.platform_data;
struct hwspinlock_device *bank;
struct hwspinlock *hwlock;
void __iomem *io_base;
int i, num_locks = U8500_MAX_SEMAPHORE;
ulong val;
if (!pdata)
return -ENODEV;
io_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(io_base))
return PTR_ERR(io_base);
/* make sure protocol 1 is selected */
val = readl(io_base + HSEM_CTRL_REG);
writel((val & ~HSEM_PROTOCOL_1), io_base + HSEM_CTRL_REG);
/* clear all interrupts */
writel(0xFFFF, io_base + HSEM_ICRALL);
bank = devm_kzalloc(&pdev->dev, struct_size(bank, lock, num_locks),
GFP_KERNEL);
if (!bank)
return -ENOMEM;
platform_set_drvdata(pdev, bank);
for (i = 0, hwlock = &bank->lock[0]; i < num_locks; i++, hwlock++)
hwlock->priv = io_base + HSEM_REGISTER_OFFSET + sizeof(u32) * i;
return devm_hwspin_lock_register(&pdev->dev, bank,
&u8500_hwspinlock_ops,
pdata->base_id, num_locks);
}
static int u8500_hsem_remove(struct platform_device *pdev)
{
struct hwspinlock_device *bank = platform_get_drvdata(pdev);
void __iomem *io_base = bank->lock[0].priv - HSEM_REGISTER_OFFSET;
/* clear all interrupts */
writel(0xFFFF, io_base + HSEM_ICRALL);
return 0;
}
static struct platform_driver u8500_hsem_driver = {
.probe = u8500_hsem_probe,
.remove = u8500_hsem_remove,
.driver = {
.name = "u8500_hsem",
},
};
static int __init u8500_hsem_init(void)
{
return platform_driver_register(&u8500_hsem_driver);
}
/* board init code might need to reserve hwspinlocks for predefined purposes */
postcore_initcall(u8500_hsem_init);
static void __exit u8500_hsem_exit(void)
{
platform_driver_unregister(&u8500_hsem_driver);
}
module_exit(u8500_hsem_exit);
MODULE_LICENSE("GPL v2");
MODULE_DESCRIPTION("Hardware Spinlock driver for u8500");
MODULE_AUTHOR("Mathieu Poirier <mathieu.poirier@linaro.org>");
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