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05 April 2024, 19:05:47 UTC
Revision 070e76cb3ffe43f6855492e77c96680c562598f0 authored by Leonid Yegoshin on 27 November 2014, 11:13:08 UTC, committed by Ralf Baechle on 27 November 2014, 16:21:56 UTC 
MIPS: tlbex: Fix potential HTW race on TLBL/M/S handlers
 
There is a potential race when probing the TLB in TLBL/M/S exception
handlers for a matching entry. Between the time we hit a TLBL/S/M
exception and the time we get to execute the TLBP instruction, the
HTW may have replaced the TLB entry we are interested in hence the TLB
probe may fail. However, in the existing handlers, we never checked the
status of the TLBP (ie check the result in the C0/Index register). We
fix this by adding such a check when the core implements the HTW. If
we couldn't find a matching entry, we return back and try again.

Signed-off-by: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Reviewed-by: James Hogan <james.hogan@imgtec.com>
Cc: <stable@vger.kernel.org> # v3.17+
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8599/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1 parent b4da18b
History
Tip revision: 070e76cb3ffe43f6855492e77c96680c562598f0 authored by Leonid Yegoshin on 27 November 2014, 11:13:08 UTC
MIPS: tlbex: Fix potential HTW race on TLBL/M/S handlers
Tip revision: 070e76c
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