https://github.com/torvalds/linux
Revision 075c733e19ce7530b53b78151cc4d303c8f64548 authored by Ralf Baechle on 05 July 2007, 07:14:21 UTC, committed by Ralf Baechle on 06 July 2007, 15:17:11 UTC
The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
opposes it being called that) where invalid instructions in the same
I-cache line worth of instructions being fetched may case spurious
exceptions.

The workaround for this was only enabled for E9000 cores; enable it also
for all RM7000-based platforms.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1 parent 9349075
History
Tip revision: 075c733e19ce7530b53b78151cc4d303c8f64548 authored by Ralf Baechle on 05 July 2007, 07:14:21 UTC
[MIPS] RM7000: Enable ICACHE_REFILLS_WORKAROUND_WAR.
Tip revision: 075c733
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usr
.gitignore -rw-r--r-- 572 bytes
.mailmap -rw-r--r-- 3.6 KB
COPYING -rw-r--r-- 18.3 KB
CREDITS -rw-r--r-- 89.3 KB
Kbuild -rw-r--r-- 1.5 KB
MAINTAINERS -rw-r--r-- 87.8 KB
Makefile -rw-r--r-- 49.2 KB
README -rw-r--r-- 16.5 KB
REPORTING-BUGS -rw-r--r-- 3.0 KB

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