Revision 075c733e19ce7530b53b78151cc4d303c8f64548 authored by Ralf Baechle on 05 July 2007, 07:14:21 UTC, committed by Ralf Baechle on 06 July 2007, 15:17:11 UTC
The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra opposes it being called that) where invalid instructions in the same I-cache line worth of instructions being fetched may case spurious exceptions. The workaround for this was only enabled for E9000 cores; enable it also for all RM7000-based platforms. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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| File | Mode | Size |
|---|---|---|
| Makefile | -rw-r--r-- | 284 bytes |
| clntlock.c | -rw-r--r-- | 5.5 KB |
| clntproc.c | -rw-r--r-- | 19.7 KB |
| host.c | -rw-r--r-- | 12.7 KB |
| mon.c | -rw-r--r-- | 5.6 KB |
| svc.c | -rw-r--r-- | 13.6 KB |
| svc4proc.c | -rw-r--r-- | 14.6 KB |
| svclock.c | -rw-r--r-- | 23.3 KB |
| svcproc.c | -rw-r--r-- | 15.2 KB |
| svcshare.c | -rw-r--r-- | 2.4 KB |
| svcsubs.c | -rw-r--r-- | 8.4 KB |
| xdr.c | -rw-r--r-- | 14.1 KB |
| xdr4.c | -rw-r--r-- | 13.8 KB |
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