Revision 0764b8a8e37a490cb01550d2b2c3cb45e073fc39 authored by Zack Buhman on 07 April 2024, 15:07:05 UTC, committed by Michael Tokarev on 10 April 2024, 17:32:12 UTC
CHECK_NOT_DELAY_SLOT is correctly applied to the branch-related
instructions, but not to the PC-relative mov* instructions.

I verified the existence of an illegal slot exception on a SH7091 when
any of these instructions are attempted inside a delay slot.

This also matches the behavior described in the SH-4 ISA manual.

Signed-off-by: Zack Buhman <zack@buhman.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20240407150705.5965-1-zack@buhman.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewd-by: Yoshinori Sato <ysato@users.sourceforge.jp>
(cherry picked from commit b754cb2dcde26a7bc8a9d17bb6900a0ac0dd38e2)
Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
1 parent 7335117
History
File Mode Size
alpha.c -rw-r--r-- 79.8 KB
capstone.c -rw-r--r-- 9.5 KB
cris.c -rw-r--r-- 80.0 KB
disas-internal.h -rw-r--r-- 440 bytes
disas-mon.c -rw-r--r-- 1.7 KB
disas.c -rw-r--r-- 9.3 KB
hexagon.c -rw-r--r-- 2.0 KB
hppa.c -rw-r--r-- 100.3 KB
m68k.c -rw-r--r-- 212.0 KB
meson.build -rw-r--r-- 1.0 KB
microblaze.c -rw-r--r-- 58.2 KB
mips.c -rw-r--r-- 268.2 KB
nanomips.c -rw-r--r-- 697.1 KB
nios2.c -rw-r--r-- 131.7 KB
riscv-xthead.c -rw-r--r-- 24.2 KB
riscv-xthead.h -rw-r--r-- 818 bytes
riscv-xventana.c -rw-r--r-- 1.0 KB
riscv-xventana.h -rw-r--r-- 379 bytes
riscv.c -rw-r--r-- 198.2 KB
riscv.h -rw-r--r-- 7.7 KB
sh4.c -rw-r--r-- 82.4 KB
sparc.c -rw-r--r-- 169.7 KB
xtensa.c -rw-r--r-- 5.0 KB

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