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17 May 2024, 11:00:25 UTC
Revision 08f051eda33b51e8ee0f45f05bcfe49d0f0caf6b authored by Andrew Waterman on 25 October 2017, 21:30:32 UTC, committed by Palmer Dabbelt on 30 November 2017, 20:58:25 UTC 
RISC-V: Flush I$ when making a dirty page executable
 
The RISC-V ISA allows for instruction caches that are not coherent WRT
stores, even on a single hart.  As a result, we need to explicitly flush
the instruction cache whenever marking a dirty page as executable in
order to preserve the correct system behavior.

Local instruction caches aren't that scary (our implementations actually
flush the cache, but RISC-V is defined to allow higher-performance
implementations to exist), but RISC-V defines no way to perform an
instruction cache shootdown.  When explicitly asked to do so we can
shoot down remote instruction caches via an IPI, but this is a bit on
the slow side.

Instead of requiring an IPI to all harts whenever marking a page as
executable, we simply flush the currently running harts.  In order to
maintain correct behavior, we additionally mark every other hart as
needing a deferred instruction cache which will be taken before anything
runs on it.

Signed-off-by: Andrew Waterman <andrew@sifive.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
1 parent 28dfbe6
History
Tip revision: 08f051eda33b51e8ee0f45f05bcfe49d0f0caf6b authored by Andrew Waterman on 25 October 2017, 21:30:32 UTC
RISC-V: Flush I$ when making a dirty page executable
Tip revision: 08f051e
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usr
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.cocciconfig -rw-r--r-- 59 bytes
.get_maintainer.ignore -rw-r--r-- 31 bytes
.gitattributes -rw-r--r-- 30 bytes
.gitignore -rw-r--r-- 1.4 KB
.mailmap -rw-r--r-- 8.8 KB
COPYING -rw-r--r-- 18.3 KB
CREDITS -rw-r--r-- 96.2 KB
Kbuild -rw-r--r-- 2.2 KB
Kconfig -rw-r--r-- 287 bytes
MAINTAINERS -rw-r--r-- 425.9 KB
Makefile -rw-r--r-- 58.3 KB
README -rw-r--r-- 722 bytes

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