Revision 09e71a6f13445974fe9b70b6d4b68ac362cd68b6 authored by Dave Jiang on 13 December 2016, 16:03:13 UTC, committed by Jon Mason on 23 December 2016, 21:10:54 UTC
The offsets for the SZ registers are wrong. Updated. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reported-by: Sandeep Mann <sandeep@purestorage.com> Tested-by: Zachary Ross <zacharyx.ross@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
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| File | Mode | Size |
|---|---|---|
| arm | ||
| Kconfig | -rw-r--r-- | 784 bytes |
| async_pf.c | -rw-r--r-- | 5.8 KB |
| async_pf.h | -rw-r--r-- | 1.1 KB |
| coalesced_mmio.c | -rw-r--r-- | 4.1 KB |
| coalesced_mmio.h | -rw-r--r-- | 845 bytes |
| eventfd.c | -rw-r--r-- | 22.4 KB |
| irqchip.c | -rw-r--r-- | 6.0 KB |
| kvm_main.c | -rw-r--r-- | 91.9 KB |
| vfio.c | -rw-r--r-- | 6.1 KB |
| vfio.h | -rw-r--r-- | 250 bytes |
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