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Revision 0af294d774a8fd7b79646d003124577f1798b585 authored by Peter Maydell on 11 January 2018, 13:25:40 UTC, committed by Michael Roth on 11 January 2018, 21:10:57 UTC 
hw/intc/arm_gic: reserved register addresses are RAZ/WI
 
The GICv2 specification says that reserved register addresses
must RAZ/WI; now that we implement external abort handling
for Arm CPUs this means we must return MEMTX_OK rather than
MEMTX_ERROR, to avoid generating a spurious guest data abort.

Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 1513183941-24300-3-git-send-email-peter.maydell@linaro.org
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
(cherry picked from commit 0cf09852015e47a5fbb974ff7ac320366afd21ee)
Signed-off-by: Michael Roth <mdroth@linux.vnet.ibm.com>
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version 2.

2) Parts of QEMU have specific licenses which are compatible with the
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are released under the GNU General Public License, version 2 or (at your
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As of July 2013, contributions under version 2 of the GNU General Public
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