Revision 16e604a437c89751dc626c9e90cf88ba93c5be64 authored by Alexandru Elisei on 07 August 2019, 09:53:20 UTC, committed by Marc Zyngier on 09 August 2019, 07:07:26 UTC
A HW mapped level sensitive interrupt asserted by a device will not be put
into the ap_list if it is disabled at the VGIC level. When it is enabled
again, it will be inserted into the ap_list and written to a list register
on guest entry regardless of the state of the device.

We could argue that this can also happen on real hardware, when the command
to enable the interrupt reached the GIC before the device had the chance to
de-assert the interrupt signal; however, we emulate the distributor and
redistributors in software and we can do better than that.

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
1 parent c69509c
Raw File
cs35l36.h
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * linux/sound/cs35l36.h -- Platform data for CS35L36
 *
 * Copyright 2018 Cirrus Logic, Inc.
 *
 * Author: James Schulman <james.schulman@cirrus.com>
 *
 */

#ifndef __CS35L36_H
#define __CS35L36_H

struct cs35l36_vpbr_cfg {
	bool is_present;
	bool vpbr_en;
	int vpbr_thld;
	int vpbr_atk_rate;
	int vpbr_atk_vol;
	int vpbr_max_attn;
	int vpbr_wait;
	int vpbr_rel_rate;
	int vpbr_mute_en;
};

struct cs35l36_platform_data {
	bool multi_amp_mode;
	bool dcm_mode;
	bool amp_pcm_inv;
	bool imon_pol_inv;
	bool vmon_pol_inv;
	int boost_ind;
	int bst_vctl;
	int bst_vctl_sel;
	int bst_ipk;
	bool extern_boost;
	int temp_warn_thld;
	int irq_drv_sel;
	int irq_gpio_sel;
	struct cs35l36_vpbr_cfg vpbr_config;
};

#endif /* __CS35L36_H */
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