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Revision 16e604a437c89751dc626c9e90cf88ba93c5be64 authored by Alexandru Elisei on 07 August 2019, 09:53:20 UTC, committed by Marc Zyngier on 09 August 2019, 07:07:26 UTC 
KVM: arm/arm64: vgic: Reevaluate level sensitive interrupts on enable
 
A HW mapped level sensitive interrupt asserted by a device will not be put
into the ap_list if it is disabled at the VGIC level. When it is enabled
again, it will be inserted into the ap_list and written to a list register
on guest entry regardless of the state of the device.

We could argue that this can also happen on real hardware, when the command
to enable the interrupt reached the GIC before the device had the chance to
de-assert the interrupt signal; however, we emulate the distributor and
redistributors in software and we can do better than that.

Signed-off-by: Alexandru Elisei <alexandru.elisei@arm.com>
Signed-off-by: Marc Zyngier <maz@kernel.org>
1 parent c69509c
Raw File
rt5665.h 
/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * linux/sound/rt5665.h -- Platform data for RT5665
 *
 * Copyright 2016 Realtek Microelectronics
 */

#ifndef __LINUX_SND_RT5665_H
#define __LINUX_SND_RT5665_H

enum rt5665_dmic1_data_pin {
	RT5665_DMIC1_NULL,
	RT5665_DMIC1_DATA_GPIO4,
	RT5665_DMIC1_DATA_IN2N,
};

enum rt5665_dmic2_data_pin {
	RT5665_DMIC2_NULL,
	RT5665_DMIC2_DATA_GPIO5,
	RT5665_DMIC2_DATA_IN2P,
};

enum rt5665_jd_src {
	RT5665_JD_NULL,
	RT5665_JD1,
};

struct rt5665_platform_data {
	bool in1_diff;
	bool in2_diff;
	bool in3_diff;
	bool in4_diff;

	int ldo1_en; /* GPIO for LDO1_EN */

	enum rt5665_dmic1_data_pin dmic1_data_pin;
	enum rt5665_dmic2_data_pin dmic2_data_pin;
	enum rt5665_jd_src jd_src;

	unsigned int sar_hs_type;
};

#endif
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