Revision 259039fa30457986929a324d769f543c1509987f authored by David S. Miller on 07 February 2020, 10:36:22 UTC, committed by David S. Miller on 07 February 2020, 10:36:22 UTC
Ong Boon Leong says: ==================== net: stmmac: general fixes for Ethernet functionality 1/5: It ensures that the previous value of GMAC_VLAN_TAG register is read first before for updating the register. 2/5: Similar to 2/6 patch but it is a fix for XGMAC_VLAN_TAG register as requested by Jose Abreu. 3/5: It ensures the GMAC IP v4.xx and above behaves correctly to:- ip link set <devname> multicast off|on 4/5: Added similar IFF_MULTICAST flag for xgmac2, similar to 4/6. 5/5: It ensures PCI platform data is using plat->phy_interface. Changes from v4:- patch 1/6 - this patch is dropped now and will take the input on handling return value from netif_set_real_num_rx| tx_queues() in future patch series. v3:- patch 1/6 - add rtnl_lock() and rtnl_unlock() for stmmac_hw_setup() called inside stmmac_resume() patch 3/6 - Added new patch to fix XGMAC_VLAN_TAG register writting v2:- patch 1/5 - added control for rtnl_lock() & rtnl_unlock() to ensure they are used forstmmac_resume() patch 4/5 - added IFF_MULTICAST flag check for xgmac to ensure multicast works correctly. v1:- - Drop v1 patches (1/7, 3/7 & 4/7) that are not valid. ==================== Signed-off-by: David S. Miller <davem@davemloft.net>
File | Mode | Size |
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Kconfig | -rw-r--r-- | 6.8 KB |
Makefile | -rw-r--r-- | 1.8 KB |
altera-cvp.c | -rw-r--r-- | 19.0 KB |
altera-fpga2sdram.c | -rw-r--r-- | 4.9 KB |
altera-freeze-bridge.c | -rw-r--r-- | 6.8 KB |
altera-hps2fpga.c | -rw-r--r-- | 5.8 KB |
altera-pr-ip-core-plat.c | -rw-r--r-- | 1.4 KB |
altera-pr-ip-core.c | -rw-r--r-- | 5.0 KB |
altera-ps-spi.c | -rw-r--r-- | 8.4 KB |
dfl-afu-dma-region.c | -rw-r--r-- | 10.5 KB |
dfl-afu-error.c | -rw-r--r-- | 5.6 KB |
dfl-afu-main.c | -rw-r--r-- | 21.7 KB |
dfl-afu-region.c | -rw-r--r-- | 4.1 KB |
dfl-afu.h | -rw-r--r-- | 3.2 KB |
dfl-fme-br.c | -rw-r--r-- | 2.5 KB |
dfl-fme-error.c | -rw-r--r-- | 9.1 KB |
dfl-fme-main.c | -rw-r--r-- | 18.5 KB |
dfl-fme-mgr.c | -rw-r--r-- | 9.2 KB |
dfl-fme-pr.c | -rw-r--r-- | 11.5 KB |
dfl-fme-pr.h | -rw-r--r-- | 2.0 KB |
dfl-fme-region.c | -rw-r--r-- | 2.1 KB |
dfl-fme.h | -rw-r--r-- | 1.2 KB |
dfl-pci.c | -rw-r--r-- | 6.9 KB |
dfl.c | -rw-r--r-- | 30.9 KB |
dfl.h | -rw-r--r-- | 13.5 KB |
fpga-bridge.c | -rw-r--r-- | 12.1 KB |
fpga-mgr.c | -rw-r--r-- | 19.0 KB |
fpga-region.c | -rw-r--r-- | 8.5 KB |
ice40-spi.c | -rw-r--r-- | 5.3 KB |
machxo2-spi.c | -rw-r--r-- | 9.3 KB |
of-fpga-region.c | -rw-r--r-- | 12.0 KB |
socfpga-a10.c | -rw-r--r-- | 15.3 KB |
socfpga.c | -rw-r--r-- | 17.0 KB |
stratix10-soc.c | -rw-r--r-- | 12.5 KB |
ts73xx-fpga.c | -rw-r--r-- | 3.8 KB |
xilinx-pr-decoupler.c | -rw-r--r-- | 3.7 KB |
xilinx-spi.c | -rw-r--r-- | 4.7 KB |
zynq-fpga.c | -rw-r--r-- | 17.2 KB |
zynqmp-fpga.c | -rw-r--r-- | 3.5 KB |
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