Revision 259039fa30457986929a324d769f543c1509987f authored by David S. Miller on 07 February 2020, 10:36:22 UTC, committed by David S. Miller on 07 February 2020, 10:36:22 UTC
Ong Boon Leong says:
====================
net: stmmac: general fixes for Ethernet functionality
1/5: It ensures that the previous value of GMAC_VLAN_TAG register is
read first before for updating the register.
2/5: Similar to 2/6 patch but it is a fix for XGMAC_VLAN_TAG register
as requested by Jose Abreu.
3/5: It ensures the GMAC IP v4.xx and above behaves correctly to:-
ip link set <devname> multicast off|on
4/5: Added similar IFF_MULTICAST flag for xgmac2, similar to 4/6.
5/5: It ensures PCI platform data is using plat->phy_interface.
Changes from v4:-
patch 1/6 - this patch is dropped now and will take the input on
handling return value from netif_set_real_num_rx|
tx_queues() in future patch series.
v3:-
patch 1/6 - add rtnl_lock() and rtnl_unlock() for stmmac_hw_setup()
called inside stmmac_resume()
patch 3/6 - Added new patch to fix XGMAC_VLAN_TAG register writting
v2:-
patch 1/5 - added control for rtnl_lock() & rtnl_unlock() to ensure
they are used forstmmac_resume()
patch 4/5 - added IFF_MULTICAST flag check for xgmac to ensure
multicast works correctly.
v1:-
- Drop v1 patches (1/7, 3/7 & 4/7) that are not valid.
====================
Signed-off-by: David S. Miller <davem@davemloft.net>
nsp32_io.h
/*
* Workbit NinjaSCSI-32Bi/UDE PCI/CardBus SCSI Host Bus Adapter driver
* I/O routine
*
* This software may be used and distributed according to the terms of
* the GNU General Public License.
*/
#ifndef _NSP32_IO_H
#define _NSP32_IO_H
static inline void nsp32_write1(unsigned int base,
unsigned int index,
unsigned char val)
{
outb(val, (base + index));
}
static inline unsigned char nsp32_read1(unsigned int base,
unsigned int index)
{
return inb(base + index);
}
static inline void nsp32_write2(unsigned int base,
unsigned int index,
unsigned short val)
{
outw(val, (base + index));
}
static inline unsigned short nsp32_read2(unsigned int base,
unsigned int index)
{
return inw(base + index);
}
static inline void nsp32_write4(unsigned int base,
unsigned int index,
unsigned long val)
{
outl(val, (base + index));
}
static inline unsigned long nsp32_read4(unsigned int base,
unsigned int index)
{
return inl(base + index);
}
/*==============================================*/
static inline void nsp32_mmio_write1(unsigned long base,
unsigned int index,
unsigned char val)
{
volatile unsigned char *ptr;
ptr = (unsigned char *)(base + NSP32_MMIO_OFFSET + index);
writeb(val, ptr);
}
static inline unsigned char nsp32_mmio_read1(unsigned long base,
unsigned int index)
{
volatile unsigned char *ptr;
ptr = (unsigned char *)(base + NSP32_MMIO_OFFSET + index);
return readb(ptr);
}
static inline void nsp32_mmio_write2(unsigned long base,
unsigned int index,
unsigned short val)
{
volatile unsigned short *ptr;
ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + index);
writew(cpu_to_le16(val), ptr);
}
static inline unsigned short nsp32_mmio_read2(unsigned long base,
unsigned int index)
{
volatile unsigned short *ptr;
ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + index);
return le16_to_cpu(readw(ptr));
}
static inline void nsp32_mmio_write4(unsigned long base,
unsigned int index,
unsigned long val)
{
volatile unsigned long *ptr;
ptr = (unsigned long *)(base + NSP32_MMIO_OFFSET + index);
writel(cpu_to_le32(val), ptr);
}
static inline unsigned long nsp32_mmio_read4(unsigned long base,
unsigned int index)
{
volatile unsigned long *ptr;
ptr = (unsigned long *)(base + NSP32_MMIO_OFFSET + index);
return le32_to_cpu(readl(ptr));
}
/*==============================================*/
static inline unsigned char nsp32_index_read1(unsigned int base,
unsigned int reg)
{
outb(reg, base + INDEX_REG);
return inb(base + DATA_REG_LOW);
}
static inline void nsp32_index_write1(unsigned int base,
unsigned int reg,
unsigned char val)
{
outb(reg, base + INDEX_REG );
outb(val, base + DATA_REG_LOW);
}
static inline unsigned short nsp32_index_read2(unsigned int base,
unsigned int reg)
{
outb(reg, base + INDEX_REG);
return inw(base + DATA_REG_LOW);
}
static inline void nsp32_index_write2(unsigned int base,
unsigned int reg,
unsigned short val)
{
outb(reg, base + INDEX_REG );
outw(val, base + DATA_REG_LOW);
}
static inline unsigned long nsp32_index_read4(unsigned int base,
unsigned int reg)
{
unsigned long h,l;
outb(reg, base + INDEX_REG);
l = inw(base + DATA_REG_LOW);
h = inw(base + DATA_REG_HI );
return ((h << 16) | l);
}
static inline void nsp32_index_write4(unsigned int base,
unsigned int reg,
unsigned long val)
{
unsigned long h,l;
h = (val & 0xffff0000) >> 16;
l = (val & 0x0000ffff) >> 0;
outb(reg, base + INDEX_REG );
outw(l, base + DATA_REG_LOW);
outw(h, base + DATA_REG_HI );
}
/*==============================================*/
static inline unsigned char nsp32_mmio_index_read1(unsigned long base,
unsigned int reg)
{
volatile unsigned short *index_ptr, *data_ptr;
index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG);
data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW);
writeb(reg, index_ptr);
return readb(data_ptr);
}
static inline void nsp32_mmio_index_write1(unsigned long base,
unsigned int reg,
unsigned char val)
{
volatile unsigned short *index_ptr, *data_ptr;
index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG);
data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW);
writeb(reg, index_ptr);
writeb(val, data_ptr );
}
static inline unsigned short nsp32_mmio_index_read2(unsigned long base,
unsigned int reg)
{
volatile unsigned short *index_ptr, *data_ptr;
index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG);
data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW);
writeb(reg, index_ptr);
return le16_to_cpu(readw(data_ptr));
}
static inline void nsp32_mmio_index_write2(unsigned long base,
unsigned int reg,
unsigned short val)
{
volatile unsigned short *index_ptr, *data_ptr;
index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG);
data_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW);
writeb(reg, index_ptr);
writew(cpu_to_le16(val), data_ptr );
}
/*==============================================*/
static inline void nsp32_multi_read4(unsigned int base,
unsigned int reg,
void *buf,
unsigned long count)
{
insl(base + reg, buf, count);
}
static inline void nsp32_fifo_read(unsigned int base,
void *buf,
unsigned long count)
{
nsp32_multi_read4(base, FIFO_DATA_LOW, buf, count);
}
static inline void nsp32_multi_write4(unsigned int base,
unsigned int reg,
void *buf,
unsigned long count)
{
outsl(base + reg, buf, count);
}
static inline void nsp32_fifo_write(unsigned int base,
void *buf,
unsigned long count)
{
nsp32_multi_write4(base, FIFO_DATA_LOW, buf, count);
}
#endif /* _NSP32_IO_H */
/* end */
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