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23 October 2021, 00:29:24 UTC
Revision 275e88b06a277ccf89d9c471a777e9b4f8c552b0 authored by Rob Herring on 18 December 2020, 14:39:05 UTC, committed by Bjorn Helgaas on 26 December 2020, 03:58:36 UTC 
PCI: tegra: Fix host link initialization
 
Commit b9ac0f9dc8ea ("PCI: dwc: Move dw_pcie_setup_rc() to DWC common
code") broke enumeration of downstream devices on Tegra:

In non-working case (next-20201211):

  0001:00:00.0 PCI bridge: NVIDIA Corporation Device 1ad2 (rev a1)
  0001:01:00.0 SATA controller: Marvell Technology Group Ltd. Device 9171 (rev 13)
  0005:00:00.0 PCI bridge: NVIDIA Corporation Device 1ad0 (rev a1)

In working case (v5.10-rc7):

  0001:00:00.0 PCI bridge: Molex Incorporated Device 1ad2 (rev a1)
  0001:01:00.0 SATA controller: Marvell Technology Group Ltd. Device 9171 (rev 13)
  0005:00:00.0 PCI bridge: Molex Incorporated Device 1ad0 (rev a1)
  0005:01:00.0 PCI bridge: PLX Technology, Inc. Device 3380 (rev ab)
  0005:02:02.0 PCI bridge: PLX Technology, Inc. Device 3380 (rev ab)
  0005:03:00.0 USB controller: PLX Technology, Inc. Device 3380 (rev ab)

The problem seems to be dw_pcie_setup_rc() is now called twice before and
after the link up handling. The fix is to move Tegra's link up handling to
.start_link() function like other DWC drivers. Tegra is a bit more
complicated than others as it re-inits the whole DWC controller to retry
the link. With this, the initialization ordering is restored to match the
prior sequence.

Fixes: b9ac0f9dc8ea ("PCI: dwc: Move dw_pcie_setup_rc() to DWC common code")
Link: https://lore.kernel.org/r/20201218143905.1614098-1-robh@kernel.org
Reported-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Tested-by: Mian Yousaf Kaukab <ykaukab@suse.de>
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Jonathan Hunter <jonathanh@nvidia.com>
Cc: Vidya Sagar <vidyas@nvidia.com>
1 parent 255b2d5
Raw File
Tip revision: 275e88b06a277ccf89d9c471a777e9b4f8c552b0 authored by Rob Herring on 18 December 2020, 14:39:05 UTC
PCI: tegra: Fix host link initialization
Tip revision: 275e88b
gpio-wcd934x.c 
// SPDX-License-Identifier: GPL-2.0
// Copyright (c) 2019, Linaro Limited

#include <linux/module.h>
#include <linux/gpio/driver.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/of_device.h>

#define WCD_PIN_MASK(p) BIT(p - 1)
#define WCD_REG_DIR_CTL_OFFSET 0x42
#define WCD_REG_VAL_CTL_OFFSET 0x43
#define WCD934X_NPINS		5

struct wcd_gpio_data {
	struct regmap *map;
	struct gpio_chip chip;
};

static int wcd_gpio_get_direction(struct gpio_chip *chip, unsigned int pin)
{
	struct wcd_gpio_data *data = gpiochip_get_data(chip);
	unsigned int value;
	int ret;

	ret = regmap_read(data->map, WCD_REG_DIR_CTL_OFFSET, &value);
	if (ret < 0)
		return ret;

	if (value & WCD_PIN_MASK(pin))
		return GPIO_LINE_DIRECTION_OUT;

	return GPIO_LINE_DIRECTION_IN;
}

static int wcd_gpio_direction_input(struct gpio_chip *chip, unsigned int pin)
{
	struct wcd_gpio_data *data = gpiochip_get_data(chip);

	return regmap_update_bits(data->map, WCD_REG_DIR_CTL_OFFSET,
				  WCD_PIN_MASK(pin), 0);
}

static int wcd_gpio_direction_output(struct gpio_chip *chip, unsigned int pin,
				     int val)
{
	struct wcd_gpio_data *data = gpiochip_get_data(chip);

	regmap_update_bits(data->map, WCD_REG_DIR_CTL_OFFSET,
			   WCD_PIN_MASK(pin), WCD_PIN_MASK(pin));

	return regmap_update_bits(data->map, WCD_REG_VAL_CTL_OFFSET,
				  WCD_PIN_MASK(pin),
				  val ? WCD_PIN_MASK(pin) : 0);
}

static int wcd_gpio_get(struct gpio_chip *chip, unsigned int pin)
{
	struct wcd_gpio_data *data = gpiochip_get_data(chip);
	unsigned int value;

	regmap_read(data->map, WCD_REG_VAL_CTL_OFFSET, &value);

	return !!(value & WCD_PIN_MASK(pin));
}

static void wcd_gpio_set(struct gpio_chip *chip, unsigned int pin, int val)
{
	struct wcd_gpio_data *data = gpiochip_get_data(chip);

	regmap_update_bits(data->map, WCD_REG_VAL_CTL_OFFSET,
			   WCD_PIN_MASK(pin), val ? WCD_PIN_MASK(pin) : 0);
}

static int wcd_gpio_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct wcd_gpio_data *data;
	struct gpio_chip *chip;

	data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	data->map = dev_get_regmap(dev->parent, NULL);
	if (!data->map) {
		dev_err(dev, "%s: failed to get regmap\n", __func__);
		return  -EINVAL;
	}

	chip = &data->chip;
	chip->direction_input  = wcd_gpio_direction_input;
	chip->direction_output = wcd_gpio_direction_output;
	chip->get_direction = wcd_gpio_get_direction;
	chip->get = wcd_gpio_get;
	chip->set = wcd_gpio_set;
	chip->parent = dev;
	chip->base = -1;
	chip->ngpio = WCD934X_NPINS;
	chip->label = dev_name(dev);
	chip->of_gpio_n_cells = 2;
	chip->can_sleep = false;

	return devm_gpiochip_add_data(dev, chip, data);
}

static const struct of_device_id wcd_gpio_of_match[] = {
	{ .compatible = "qcom,wcd9340-gpio" },
	{ .compatible = "qcom,wcd9341-gpio" },
	{ }
};
MODULE_DEVICE_TABLE(of, wcd_gpio_of_match);

static struct platform_driver wcd_gpio_driver = {
	.driver = {
		   .name = "wcd934x-gpio",
		   .of_match_table = wcd_gpio_of_match,
	},
	.probe = wcd_gpio_probe,
};

module_platform_driver(wcd_gpio_driver);
MODULE_DESCRIPTION("Qualcomm Technologies, Inc WCD GPIO control driver");
MODULE_LICENSE("GPL v2");
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