https://github.com/torvalds/linux
Revision 285994a62c80f1d72c6924282bcb59608098d5ec authored by Catalin Marinas on 11 March 2015, 12:20:39 UTC, committed by Catalin Marinas on 14 March 2015, 10:48:30 UTC
The ARM architecture allows the caching of intermediate page table
levels and page table freeing requires a sequence like:

	pmd_clear()
	TLB invalidation
	pte page freeing

With commit 5e5f6dc10546 (arm64: mm: enable HAVE_RCU_TABLE_FREE logic),
the page table freeing batching was moved from tlb_remove_page() to
tlb_remove_table(). The former takes care of TLB invalidation as this is
also shared with pte clearing and page cache page freeing. The latter,
however, does not invalidate the TLBs for intermediate page table levels
as it probably relies on the architecture code to do it if required.
When the mm->mm_users < 2, tlb_remove_table() does not do any batching
and page table pages are freed before tlb_finish_mmu() which performs
the actual TLB invalidation.

This patch introduces __tlb_flush_pgtable() for arm64 and calls it from
the {pte,pmd,pud}_free_tlb() directly without relying on deferred page
table freeing.

Fixes: 5e5f6dc10546 arm64: mm: enable HAVE_RCU_TABLE_FREE logic
Reported-by: Jon Masters <jcm@redhat.com>
Tested-by: Jon Masters <jcm@redhat.com>
Tested-by: Steve Capper <steve.capper@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
1 parent 9eccca0
History
Tip revision: 285994a62c80f1d72c6924282bcb59608098d5ec authored by Catalin Marinas on 11 March 2015, 12:20:39 UTC
arm64: Invalidate the TLB corresponding to intermediate page table levels
Tip revision: 285994a
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