Revision 28d6f93d201d20ce47a9e8414655569a78f0353c authored by Markos Chandras on 08 January 2015, 11:55:20 UTC, committed by Markos Chandras on 17 February 2015, 15:37:35 UTC
MIPS R6 uses the <R6 sdc2 opcode for the new BNEZC and JIALC instructions Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
1 parent 69b9a2f
gpio-dwapb.c
/*
* Copyright (c) 2011 Jamie Iles
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* All enquiries to support@picochip.com
*/
#include <linux/basic_mmio_gpio.h>
#include <linux/err.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/io.h>
#include <linux/ioport.h>
#include <linux/irq.h>
#include <linux/irqdomain.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/platform_device.h>
#include <linux/spinlock.h>
#include <linux/platform_data/gpio-dwapb.h>
#include <linux/slab.h>
#define GPIO_SWPORTA_DR 0x00
#define GPIO_SWPORTA_DDR 0x04
#define GPIO_SWPORTB_DR 0x0c
#define GPIO_SWPORTB_DDR 0x10
#define GPIO_SWPORTC_DR 0x18
#define GPIO_SWPORTC_DDR 0x1c
#define GPIO_SWPORTD_DR 0x24
#define GPIO_SWPORTD_DDR 0x28
#define GPIO_INTEN 0x30
#define GPIO_INTMASK 0x34
#define GPIO_INTTYPE_LEVEL 0x38
#define GPIO_INT_POLARITY 0x3c
#define GPIO_INTSTATUS 0x40
#define GPIO_PORTA_DEBOUNCE 0x48
#define GPIO_PORTA_EOI 0x4c
#define GPIO_EXT_PORTA 0x50
#define GPIO_EXT_PORTB 0x54
#define GPIO_EXT_PORTC 0x58
#define GPIO_EXT_PORTD 0x5c
#define DWAPB_MAX_PORTS 4
#define GPIO_EXT_PORT_SIZE (GPIO_EXT_PORTB - GPIO_EXT_PORTA)
#define GPIO_SWPORT_DR_SIZE (GPIO_SWPORTB_DR - GPIO_SWPORTA_DR)
#define GPIO_SWPORT_DDR_SIZE (GPIO_SWPORTB_DDR - GPIO_SWPORTA_DDR)
struct dwapb_gpio;
#ifdef CONFIG_PM_SLEEP
/* Store GPIO context across system-wide suspend/resume transitions */
struct dwapb_context {
u32 data;
u32 dir;
u32 ext;
u32 int_en;
u32 int_mask;
u32 int_type;
u32 int_pol;
u32 int_deb;
};
#endif
struct dwapb_gpio_port {
struct bgpio_chip bgc;
bool is_registered;
struct dwapb_gpio *gpio;
#ifdef CONFIG_PM_SLEEP
struct dwapb_context *ctx;
#endif
unsigned int idx;
};
struct dwapb_gpio {
struct device *dev;
void __iomem *regs;
struct dwapb_gpio_port *ports;
unsigned int nr_ports;
struct irq_domain *domain;
};
static inline struct dwapb_gpio_port *
to_dwapb_gpio_port(struct bgpio_chip *bgc)
{
return container_of(bgc, struct dwapb_gpio_port, bgc);
}
static inline u32 dwapb_read(struct dwapb_gpio *gpio, unsigned int offset)
{
struct bgpio_chip *bgc = &gpio->ports[0].bgc;
void __iomem *reg_base = gpio->regs;
return bgc->read_reg(reg_base + offset);
}
static inline void dwapb_write(struct dwapb_gpio *gpio, unsigned int offset,
u32 val)
{
struct bgpio_chip *bgc = &gpio->ports[0].bgc;
void __iomem *reg_base = gpio->regs;
bgc->write_reg(reg_base + offset, val);
}
static int dwapb_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
{
struct bgpio_chip *bgc = to_bgpio_chip(gc);
struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
struct dwapb_gpio *gpio = port->gpio;
return irq_find_mapping(gpio->domain, offset);
}
static void dwapb_toggle_trigger(struct dwapb_gpio *gpio, unsigned int offs)
{
u32 v = dwapb_read(gpio, GPIO_INT_POLARITY);
if (gpio_get_value(gpio->ports[0].bgc.gc.base + offs))
v &= ~BIT(offs);
else
v |= BIT(offs);
dwapb_write(gpio, GPIO_INT_POLARITY, v);
}
static u32 dwapb_do_irq(struct dwapb_gpio *gpio)
{
u32 irq_status = readl_relaxed(gpio->regs + GPIO_INTSTATUS);
u32 ret = irq_status;
while (irq_status) {
int hwirq = fls(irq_status) - 1;
int gpio_irq = irq_find_mapping(gpio->domain, hwirq);
generic_handle_irq(gpio_irq);
irq_status &= ~BIT(hwirq);
if ((irq_get_trigger_type(gpio_irq) & IRQ_TYPE_SENSE_MASK)
== IRQ_TYPE_EDGE_BOTH)
dwapb_toggle_trigger(gpio, hwirq);
}
return ret;
}
static void dwapb_irq_handler(u32 irq, struct irq_desc *desc)
{
struct dwapb_gpio *gpio = irq_get_handler_data(irq);
struct irq_chip *chip = irq_desc_get_chip(desc);
dwapb_do_irq(gpio);
if (chip->irq_eoi)
chip->irq_eoi(irq_desc_get_irq_data(desc));
}
static void dwapb_irq_enable(struct irq_data *d)
{
struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
struct dwapb_gpio *gpio = igc->private;
struct bgpio_chip *bgc = &gpio->ports[0].bgc;
unsigned long flags;
u32 val;
spin_lock_irqsave(&bgc->lock, flags);
val = dwapb_read(gpio, GPIO_INTEN);
val |= BIT(d->hwirq);
dwapb_write(gpio, GPIO_INTEN, val);
spin_unlock_irqrestore(&bgc->lock, flags);
}
static void dwapb_irq_disable(struct irq_data *d)
{
struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
struct dwapb_gpio *gpio = igc->private;
struct bgpio_chip *bgc = &gpio->ports[0].bgc;
unsigned long flags;
u32 val;
spin_lock_irqsave(&bgc->lock, flags);
val = dwapb_read(gpio, GPIO_INTEN);
val &= ~BIT(d->hwirq);
dwapb_write(gpio, GPIO_INTEN, val);
spin_unlock_irqrestore(&bgc->lock, flags);
}
static int dwapb_irq_reqres(struct irq_data *d)
{
struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
struct dwapb_gpio *gpio = igc->private;
struct bgpio_chip *bgc = &gpio->ports[0].bgc;
if (gpiochip_lock_as_irq(&bgc->gc, irqd_to_hwirq(d))) {
dev_err(gpio->dev, "unable to lock HW IRQ %lu for IRQ\n",
irqd_to_hwirq(d));
return -EINVAL;
}
return 0;
}
static void dwapb_irq_relres(struct irq_data *d)
{
struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
struct dwapb_gpio *gpio = igc->private;
struct bgpio_chip *bgc = &gpio->ports[0].bgc;
gpiochip_unlock_as_irq(&bgc->gc, irqd_to_hwirq(d));
}
static int dwapb_irq_set_type(struct irq_data *d, u32 type)
{
struct irq_chip_generic *igc = irq_data_get_irq_chip_data(d);
struct dwapb_gpio *gpio = igc->private;
struct bgpio_chip *bgc = &gpio->ports[0].bgc;
int bit = d->hwirq;
unsigned long level, polarity, flags;
if (type & ~(IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING |
IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW))
return -EINVAL;
spin_lock_irqsave(&bgc->lock, flags);
level = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
polarity = dwapb_read(gpio, GPIO_INT_POLARITY);
switch (type) {
case IRQ_TYPE_EDGE_BOTH:
level |= BIT(bit);
dwapb_toggle_trigger(gpio, bit);
break;
case IRQ_TYPE_EDGE_RISING:
level |= BIT(bit);
polarity |= BIT(bit);
break;
case IRQ_TYPE_EDGE_FALLING:
level |= BIT(bit);
polarity &= ~BIT(bit);
break;
case IRQ_TYPE_LEVEL_HIGH:
level &= ~BIT(bit);
polarity |= BIT(bit);
break;
case IRQ_TYPE_LEVEL_LOW:
level &= ~BIT(bit);
polarity &= ~BIT(bit);
break;
}
irq_setup_alt_chip(d, type);
dwapb_write(gpio, GPIO_INTTYPE_LEVEL, level);
dwapb_write(gpio, GPIO_INT_POLARITY, polarity);
spin_unlock_irqrestore(&bgc->lock, flags);
return 0;
}
static int dwapb_gpio_set_debounce(struct gpio_chip *gc,
unsigned offset, unsigned debounce)
{
struct bgpio_chip *bgc = to_bgpio_chip(gc);
struct dwapb_gpio_port *port = to_dwapb_gpio_port(bgc);
struct dwapb_gpio *gpio = port->gpio;
unsigned long flags, val_deb;
unsigned long mask = bgc->pin2mask(bgc, offset);
spin_lock_irqsave(&bgc->lock, flags);
val_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
if (debounce)
dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb | mask);
else
dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, val_deb & ~mask);
spin_unlock_irqrestore(&bgc->lock, flags);
return 0;
}
static irqreturn_t dwapb_irq_handler_mfd(int irq, void *dev_id)
{
u32 worked;
struct dwapb_gpio *gpio = dev_id;
worked = dwapb_do_irq(gpio);
return worked ? IRQ_HANDLED : IRQ_NONE;
}
static void dwapb_configure_irqs(struct dwapb_gpio *gpio,
struct dwapb_gpio_port *port,
struct dwapb_port_property *pp)
{
struct gpio_chip *gc = &port->bgc.gc;
struct device_node *node = pp->node;
struct irq_chip_generic *irq_gc = NULL;
unsigned int hwirq, ngpio = gc->ngpio;
struct irq_chip_type *ct;
int err, i;
gpio->domain = irq_domain_add_linear(node, ngpio,
&irq_generic_chip_ops, gpio);
if (!gpio->domain)
return;
err = irq_alloc_domain_generic_chips(gpio->domain, ngpio, 2,
"gpio-dwapb", handle_level_irq,
IRQ_NOREQUEST, 0,
IRQ_GC_INIT_NESTED_LOCK);
if (err) {
dev_info(gpio->dev, "irq_alloc_domain_generic_chips failed\n");
irq_domain_remove(gpio->domain);
gpio->domain = NULL;
return;
}
irq_gc = irq_get_domain_generic_chip(gpio->domain, 0);
if (!irq_gc) {
irq_domain_remove(gpio->domain);
gpio->domain = NULL;
return;
}
irq_gc->reg_base = gpio->regs;
irq_gc->private = gpio;
for (i = 0; i < 2; i++) {
ct = &irq_gc->chip_types[i];
ct->chip.irq_ack = irq_gc_ack_set_bit;
ct->chip.irq_mask = irq_gc_mask_set_bit;
ct->chip.irq_unmask = irq_gc_mask_clr_bit;
ct->chip.irq_set_type = dwapb_irq_set_type;
ct->chip.irq_enable = dwapb_irq_enable;
ct->chip.irq_disable = dwapb_irq_disable;
ct->chip.irq_request_resources = dwapb_irq_reqres;
ct->chip.irq_release_resources = dwapb_irq_relres;
ct->regs.ack = GPIO_PORTA_EOI;
ct->regs.mask = GPIO_INTMASK;
ct->type = IRQ_TYPE_LEVEL_MASK;
}
irq_gc->chip_types[0].type = IRQ_TYPE_LEVEL_MASK;
irq_gc->chip_types[1].type = IRQ_TYPE_EDGE_BOTH;
irq_gc->chip_types[1].handler = handle_edge_irq;
if (!pp->irq_shared) {
irq_set_chained_handler(pp->irq, dwapb_irq_handler);
irq_set_handler_data(pp->irq, gpio);
} else {
/*
* Request a shared IRQ since where MFD would have devices
* using the same irq pin
*/
err = devm_request_irq(gpio->dev, pp->irq,
dwapb_irq_handler_mfd,
IRQF_SHARED, "gpio-dwapb-mfd", gpio);
if (err) {
dev_err(gpio->dev, "error requesting IRQ\n");
irq_domain_remove(gpio->domain);
gpio->domain = NULL;
return;
}
}
for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
irq_create_mapping(gpio->domain, hwirq);
port->bgc.gc.to_irq = dwapb_gpio_to_irq;
}
static void dwapb_irq_teardown(struct dwapb_gpio *gpio)
{
struct dwapb_gpio_port *port = &gpio->ports[0];
struct gpio_chip *gc = &port->bgc.gc;
unsigned int ngpio = gc->ngpio;
irq_hw_number_t hwirq;
if (!gpio->domain)
return;
for (hwirq = 0 ; hwirq < ngpio ; hwirq++)
irq_dispose_mapping(irq_find_mapping(gpio->domain, hwirq));
irq_domain_remove(gpio->domain);
gpio->domain = NULL;
}
static int dwapb_gpio_add_port(struct dwapb_gpio *gpio,
struct dwapb_port_property *pp,
unsigned int offs)
{
struct dwapb_gpio_port *port;
void __iomem *dat, *set, *dirout;
int err;
port = &gpio->ports[offs];
port->gpio = gpio;
port->idx = pp->idx;
#ifdef CONFIG_PM_SLEEP
port->ctx = devm_kzalloc(gpio->dev, sizeof(*port->ctx), GFP_KERNEL);
if (!port->ctx)
return -ENOMEM;
#endif
dat = gpio->regs + GPIO_EXT_PORTA + (pp->idx * GPIO_EXT_PORT_SIZE);
set = gpio->regs + GPIO_SWPORTA_DR + (pp->idx * GPIO_SWPORT_DR_SIZE);
dirout = gpio->regs + GPIO_SWPORTA_DDR +
(pp->idx * GPIO_SWPORT_DDR_SIZE);
err = bgpio_init(&port->bgc, gpio->dev, 4, dat, set, NULL, dirout,
NULL, false);
if (err) {
dev_err(gpio->dev, "failed to init gpio chip for %s\n",
pp->name);
return err;
}
#ifdef CONFIG_OF_GPIO
port->bgc.gc.of_node = pp->node;
#endif
port->bgc.gc.ngpio = pp->ngpio;
port->bgc.gc.base = pp->gpio_base;
/* Only port A support debounce */
if (pp->idx == 0)
port->bgc.gc.set_debounce = dwapb_gpio_set_debounce;
if (pp->irq)
dwapb_configure_irqs(gpio, port, pp);
err = gpiochip_add(&port->bgc.gc);
if (err)
dev_err(gpio->dev, "failed to register gpiochip for %s\n",
pp->name);
else
port->is_registered = true;
return err;
}
static void dwapb_gpio_unregister(struct dwapb_gpio *gpio)
{
unsigned int m;
for (m = 0; m < gpio->nr_ports; ++m)
if (gpio->ports[m].is_registered)
gpiochip_remove(&gpio->ports[m].bgc.gc);
}
static struct dwapb_platform_data *
dwapb_gpio_get_pdata_of(struct device *dev)
{
struct device_node *node, *port_np;
struct dwapb_platform_data *pdata;
struct dwapb_port_property *pp;
int nports;
int i;
node = dev->of_node;
if (!IS_ENABLED(CONFIG_OF_GPIO) || !node)
return ERR_PTR(-ENODEV);
nports = of_get_child_count(node);
if (nports == 0)
return ERR_PTR(-ENODEV);
pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
if (!pdata)
return ERR_PTR(-ENOMEM);
pdata->properties = kcalloc(nports, sizeof(*pp), GFP_KERNEL);
if (!pdata->properties) {
kfree(pdata);
return ERR_PTR(-ENOMEM);
}
pdata->nports = nports;
i = 0;
for_each_child_of_node(node, port_np) {
pp = &pdata->properties[i++];
pp->node = port_np;
if (of_property_read_u32(port_np, "reg", &pp->idx) ||
pp->idx >= DWAPB_MAX_PORTS) {
dev_err(dev, "missing/invalid port index for %s\n",
port_np->full_name);
kfree(pdata->properties);
kfree(pdata);
return ERR_PTR(-EINVAL);
}
if (of_property_read_u32(port_np, "snps,nr-gpios",
&pp->ngpio)) {
dev_info(dev, "failed to get number of gpios for %s\n",
port_np->full_name);
pp->ngpio = 32;
}
/*
* Only port A can provide interrupts in all configurations of
* the IP.
*/
if (pp->idx == 0 &&
of_property_read_bool(port_np, "interrupt-controller")) {
pp->irq = irq_of_parse_and_map(port_np, 0);
if (!pp->irq) {
dev_warn(dev, "no irq for bank %s\n",
port_np->full_name);
}
}
pp->irq_shared = false;
pp->gpio_base = -1;
pp->name = port_np->full_name;
}
return pdata;
}
static inline void dwapb_free_pdata_of(struct dwapb_platform_data *pdata)
{
if (!IS_ENABLED(CONFIG_OF_GPIO) || !pdata)
return;
kfree(pdata->properties);
kfree(pdata);
}
static int dwapb_gpio_probe(struct platform_device *pdev)
{
unsigned int i;
struct resource *res;
struct dwapb_gpio *gpio;
int err;
struct device *dev = &pdev->dev;
struct dwapb_platform_data *pdata = dev_get_platdata(dev);
bool is_pdata_alloc = !pdata;
if (is_pdata_alloc) {
pdata = dwapb_gpio_get_pdata_of(dev);
if (IS_ERR(pdata))
return PTR_ERR(pdata);
}
if (!pdata->nports) {
err = -ENODEV;
goto out_err;
}
gpio = devm_kzalloc(&pdev->dev, sizeof(*gpio), GFP_KERNEL);
if (!gpio) {
err = -ENOMEM;
goto out_err;
}
gpio->dev = &pdev->dev;
gpio->nr_ports = pdata->nports;
gpio->ports = devm_kcalloc(&pdev->dev, gpio->nr_ports,
sizeof(*gpio->ports), GFP_KERNEL);
if (!gpio->ports) {
err = -ENOMEM;
goto out_err;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
gpio->regs = devm_ioremap_resource(&pdev->dev, res);
if (IS_ERR(gpio->regs)) {
err = PTR_ERR(gpio->regs);
goto out_err;
}
for (i = 0; i < gpio->nr_ports; i++) {
err = dwapb_gpio_add_port(gpio, &pdata->properties[i], i);
if (err)
goto out_unregister;
}
platform_set_drvdata(pdev, gpio);
goto out_err;
out_unregister:
dwapb_gpio_unregister(gpio);
dwapb_irq_teardown(gpio);
out_err:
if (is_pdata_alloc)
dwapb_free_pdata_of(pdata);
return err;
}
static int dwapb_gpio_remove(struct platform_device *pdev)
{
struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
dwapb_gpio_unregister(gpio);
dwapb_irq_teardown(gpio);
return 0;
}
static const struct of_device_id dwapb_of_match[] = {
{ .compatible = "snps,dw-apb-gpio" },
{ /* Sentinel */ }
};
MODULE_DEVICE_TABLE(of, dwapb_of_match);
#ifdef CONFIG_PM_SLEEP
static int dwapb_gpio_suspend(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
struct bgpio_chip *bgc = &gpio->ports[0].bgc;
unsigned long flags;
int i;
spin_lock_irqsave(&bgc->lock, flags);
for (i = 0; i < gpio->nr_ports; i++) {
unsigned int offset;
unsigned int idx = gpio->ports[i].idx;
struct dwapb_context *ctx = gpio->ports[i].ctx;
BUG_ON(!ctx);
offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
ctx->dir = dwapb_read(gpio, offset);
offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
ctx->data = dwapb_read(gpio, offset);
offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
ctx->ext = dwapb_read(gpio, offset);
/* Only port A can provide interrupts */
if (idx == 0) {
ctx->int_mask = dwapb_read(gpio, GPIO_INTMASK);
ctx->int_en = dwapb_read(gpio, GPIO_INTEN);
ctx->int_pol = dwapb_read(gpio, GPIO_INT_POLARITY);
ctx->int_type = dwapb_read(gpio, GPIO_INTTYPE_LEVEL);
ctx->int_deb = dwapb_read(gpio, GPIO_PORTA_DEBOUNCE);
/* Mask out interrupts */
dwapb_write(gpio, GPIO_INTMASK, 0xffffffff);
}
}
spin_unlock_irqrestore(&bgc->lock, flags);
return 0;
}
static int dwapb_gpio_resume(struct device *dev)
{
struct platform_device *pdev = to_platform_device(dev);
struct dwapb_gpio *gpio = platform_get_drvdata(pdev);
struct bgpio_chip *bgc = &gpio->ports[0].bgc;
unsigned long flags;
int i;
spin_lock_irqsave(&bgc->lock, flags);
for (i = 0; i < gpio->nr_ports; i++) {
unsigned int offset;
unsigned int idx = gpio->ports[i].idx;
struct dwapb_context *ctx = gpio->ports[i].ctx;
BUG_ON(!ctx);
offset = GPIO_SWPORTA_DR + idx * GPIO_SWPORT_DR_SIZE;
dwapb_write(gpio, offset, ctx->data);
offset = GPIO_SWPORTA_DDR + idx * GPIO_SWPORT_DDR_SIZE;
dwapb_write(gpio, offset, ctx->dir);
offset = GPIO_EXT_PORTA + idx * GPIO_EXT_PORT_SIZE;
dwapb_write(gpio, offset, ctx->ext);
/* Only port A can provide interrupts */
if (idx == 0) {
dwapb_write(gpio, GPIO_INTTYPE_LEVEL, ctx->int_type);
dwapb_write(gpio, GPIO_INT_POLARITY, ctx->int_pol);
dwapb_write(gpio, GPIO_PORTA_DEBOUNCE, ctx->int_deb);
dwapb_write(gpio, GPIO_INTEN, ctx->int_en);
dwapb_write(gpio, GPIO_INTMASK, ctx->int_mask);
/* Clear out spurious interrupts */
dwapb_write(gpio, GPIO_PORTA_EOI, 0xffffffff);
}
}
spin_unlock_irqrestore(&bgc->lock, flags);
return 0;
}
#endif
static SIMPLE_DEV_PM_OPS(dwapb_gpio_pm_ops, dwapb_gpio_suspend,
dwapb_gpio_resume);
static struct platform_driver dwapb_gpio_driver = {
.driver = {
.name = "gpio-dwapb",
.pm = &dwapb_gpio_pm_ops,
.of_match_table = of_match_ptr(dwapb_of_match),
},
.probe = dwapb_gpio_probe,
.remove = dwapb_gpio_remove,
};
module_platform_driver(dwapb_gpio_driver);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Jamie Iles");
MODULE_DESCRIPTION("Synopsys DesignWare APB GPIO driver");
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