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23 October 2021, 00:29:24 UTC
Revision 31a3a7b5b26f75fbe82de10ca99f2b673f6c26b4 authored by Shawn Lin on 10 November 2016, 17:14:37 UTC, committed by Bjorn Helgaas on 10 November 2016, 17:14:37 UTC 
PCI: rockchip: Add three new resets as required properties
 
pm_rst, aclk_rst, pclk_rst was controlled by ROM code so the software
wasn't needed to control it again in theory.  But it didn't work properly,
so we do need to do it again and add enough delay between the assert of
pm_rst and the deassert of pm_rst.  The Soc intergrated with this
controller, rk3399, is still under MP test internally, so the backward
compatibility won't be a big deal.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
1 parent 16d917b
History
Tip revision: 31a3a7b5b26f75fbe82de10ca99f2b673f6c26b4 authored by Shawn Lin on 10 November 2016, 17:14:37 UTC
PCI: rockchip: Add three new resets as required properties
Tip revision: 31a3a7b
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