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05 April 2024, 19:05:47 UTC
Revision 3274c5707c22221574b396d140d0db3480a2027a authored by Michal Simek on 26 April 2010, 06:54:13 UTC, committed by Michal Simek on 06 May 2010, 09:22:00 UTC 
microblaze: Optimize CACHE_LOOP_LIMITS and CACHE_RANGE_LOOP macros
 
1. Remove CACHE_ALL_LOOP2 macro because it is identical to CACHE_ALL_LOOP
2. Change BUG_ON to WARN_ON
3. Remove end aligned from CACHE_LOOP_LIMITS.
C implementation do not need aligned end address and ASM code do aligned
in their macros
4. ASM optimized  CACHE_RANGE_LOOP_1/2 macros needs to get aligned end address.
Because end address is compound from start + size, end address is the first address
which is exclude.

Here is the corresponding code which describe it.
+       int align = ~(line_length - 1);
+       end = ((end & align) == end) ? end - line_length : end & align;

a) end is aligned:
it is necessary to subtruct line length because we don't want to work with
next cacheline
b) end address is not aligned:
Just align it to be ready for ASM code.

Signed-off-by: Michal Simek <monstr@monstr.eu>
1 parent 385e1ef
History
Tip revision: 3274c5707c22221574b396d140d0db3480a2027a authored by Michal Simek on 26 April 2010, 06:54:13 UTC
microblaze: Optimize CACHE_LOOP_LIMITS and CACHE_RANGE_LOOP macros
Tip revision: 3274c57
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