Revision 34f7145a63211eb7ecfcafa6c2a8db5646baf953 authored by Phil Edworthy on 24 August 2011, 10:43:59 UTC, committed by Paul Mundt on 29 August 2011, 06:32:10 UTC
This adds unaligned memory access support for the following instructions: mov.w @(disp,PC),Rn mov.l @(disp,PC),Rn These instructions are often used on SH2A toolchains. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
1 parent 0710b91
cache.h
#ifndef __ASM_GENERIC_CACHE_H
#define __ASM_GENERIC_CACHE_H
/*
* 32 bytes appears to be the most common cache line size,
* so make that the default here. Architectures with larger
* cache lines need to provide their own cache.h.
*/
#define L1_CACHE_SHIFT 5
#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
#endif /* __ASM_GENERIC_CACHE_H */
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