Revision 38aa4a568ba4c3ccba83e862a01e3e60e3b811ee authored by Alex Deucher on 08 March 2012, 00:05:01 UTC, committed by Dave Airlie on 08 March 2012, 09:39:54 UTC
All pre-SI chips are limited to 165 Mhz for single link. Code in question will be re-enabled when SI support is added. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=44755 https://bugzilla.kernel.org/show_bug.cgi?id=42887 Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Signed-off-by: Dave Airlie <airlied@redhat.com>
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| File | Mode | Size |
|---|---|---|
| Kconfig.cache | -rw-r--r-- | 4.5 KB |
| Makefile | -rw-r--r-- | 1.2 KB |
| cache-dbg-flush-by-reg.S | -rw-r--r-- | 3.5 KB |
| cache-dbg-flush-by-tag.S | -rw-r--r-- | 3.2 KB |
| cache-dbg-inv-by-reg.S | -rw-r--r-- | 1.7 KB |
| cache-dbg-inv-by-tag.S | -rw-r--r-- | 3.1 KB |
| cache-dbg-inv.S | -rw-r--r-- | 1.3 KB |
| cache-disabled.c | -rw-r--r-- | 606 bytes |
| cache-flush-by-reg.S | -rw-r--r-- | 7.6 KB |
| cache-flush-by-tag.S | -rw-r--r-- | 7.7 KB |
| cache-flush-icache.c | -rw-r--r-- | 4.3 KB |
| cache-inv-by-reg.S | -rw-r--r-- | 8.3 KB |
| cache-inv-by-tag.S | -rw-r--r-- | 7.8 KB |
| cache-inv-icache.c | -rw-r--r-- | 3.6 KB |
| cache-smp-flush.c | -rw-r--r-- | 4.5 KB |
| cache-smp-inv.c | -rw-r--r-- | 4.3 KB |
| cache-smp.c | -rw-r--r-- | 2.9 KB |
| cache-smp.h | -rw-r--r-- | 1.8 KB |
| cache.c | -rw-r--r-- | 1.6 KB |
| cache.inc | -rw-r--r-- | 2.6 KB |
| dma-alloc.c | -rw-r--r-- | 2.0 KB |
| extable.c | -rw-r--r-- | 705 bytes |
| fault.c | -rw-r--r-- | 9.7 KB |
| init.c | -rw-r--r-- | 4.9 KB |
| misalignment.c | -rw-r--r-- | 29.3 KB |
| mmu-context.c | -rw-r--r-- | 1.6 KB |
| pgtable.c | -rw-r--r-- | 4.6 KB |
| tlb-mn10300.S | -rw-r--r-- | 5.0 KB |
| tlb-smp.c | -rw-r--r-- | 5.1 KB |
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