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Revision 3d65492a86d4e6675734646929759138a023d914 authored by Roi Dayan on 17 January 2022, 13:00:30 UTC, committed by Saeed Mahameed on 24 February 2022, 00:08:17 UTC 
net/mlx5e: TC, Reject rules with forward and drop actions
 
Such rules are redundant but allowed and passed to the driver.
The driver does not support offloading such rules so return an error.

Fixes: 03a9d11e6eeb ("net/mlx5e: Add TC drop and mirred/redirect action parsing for SRIOV offloads")
Signed-off-by: Roi Dayan <roid@nvidia.com>
Reviewed-by: Oz Shlomo <ozsh@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
1 parent 23216d3
Raw File
fsl_aud2htx.h 
/* SPDX-License-Identifier: GPL-2.0 */
/*
 * Copyright 2020 NXP
 */

#ifndef _FSL_AUD2HTX_H
#define _FSL_AUD2HTX_H

#define FSL_AUD2HTX_FORMATS (SNDRV_PCM_FMTBIT_S24_LE | \
			     SNDRV_PCM_FMTBIT_S32_LE)

/* AUD2HTX Register Map */
#define AUD2HTX_CTRL          0x0   /* AUD2HTX Control Register */
#define AUD2HTX_CTRL_EXT      0x4   /* AUD2HTX Control Extended Register */
#define AUD2HTX_WR            0x8   /* AUD2HTX Write Register */
#define AUD2HTX_STATUS        0xC   /* AUD2HTX Status Register */
#define AUD2HTX_IRQ_NOMASK    0x10  /* AUD2HTX Nonmasked Interrupt Flags Register */
#define AUD2HTX_IRQ_MASKED    0x14  /* AUD2HTX Masked Interrupt Flags Register */
#define AUD2HTX_IRQ_MASK      0x18  /* AUD2HTX IRQ Masks Register */

/* AUD2HTX Control Register */
#define AUD2HTX_CTRL_EN          BIT(0)

/* AUD2HTX Control Extended Register */
#define AUD2HTX_CTRE_DE          BIT(0)
#define AUD2HTX_CTRE_DT_SHIFT    0x1
#define AUD2HTX_CTRE_DT_WIDTH    0x2
#define AUD2HTX_CTRE_DT_MASK     ((BIT(AUD2HTX_CTRE_DT_WIDTH) - 1) \
				 << AUD2HTX_CTRE_DT_SHIFT)
#define AUD2HTX_CTRE_WL_SHIFT    16
#define AUD2HTX_CTRE_WL_WIDTH    5
#define AUD2HTX_CTRE_WL_MASK     ((BIT(AUD2HTX_CTRE_WL_WIDTH) - 1) \
				 << AUD2HTX_CTRE_WL_SHIFT)
#define AUD2HTX_CTRE_WH_SHIFT    24
#define AUD2HTX_CTRE_WH_WIDTH    5
#define AUD2HTX_CTRE_WH_MASK     ((BIT(AUD2HTX_CTRE_WH_WIDTH) - 1) \
				 << AUD2HTX_CTRE_WH_SHIFT)

/* AUD2HTX IRQ Masks Register */
#define AUD2HTX_WM_HIGH_IRQ_MASK BIT(2)
#define AUD2HTX_WM_LOW_IRQ_MASK  BIT(1)
#define AUD2HTX_OVF_MASK         BIT(0)

#define AUD2HTX_FIFO_DEPTH       0x20
#define AUD2HTX_WTMK_LOW         0x10
#define AUD2HTX_WTMK_HIGH        0x10
#define AUD2HTX_MAXBURST         0x10

/**
 * fsl_aud2htx: AUD2HTX private data
 *
 * @pdev: platform device pointer
 * @regmap: regmap handler
 * @bus_clk: clock source to access register
 * @dma_params_rx: DMA parameters for receive channel
 * @dma_params_tx: DMA parameters for transmit channel
 */
struct fsl_aud2htx {
	struct platform_device *pdev;
	struct regmap *regmap;
	struct clk *bus_clk;

	struct snd_dmaengine_dai_dma_data dma_params_rx;
	struct snd_dmaengine_dai_dma_data dma_params_tx;
};

#endif /* _FSL_AUD2HTX_H */
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