Revision 3dbcea54b3ff706c58f8e8d4470f5e5d3d24a6a0 authored by Mark Rutland on 15 March 2019, 12:22:36 UTC, committed by Catalin Marinas on 19 March 2019, 14:54:24 UTC
Fujitsu erratum 010001 applies to A64FX v0r0 and v1r0, and we try to
handle either by masking MIDR with MIDR_FUJITSU_ERRATUM_010001_MASK
before comparing it to MIDR_FUJITSU_ERRATUM_010001.
Unfortunately, MIDR_FUJITSU_ERRATUM_010001 is constructed incorrectly
using MIDR_VARIANT(), which is intended to extract the variant field
from MIDR_EL1, rather than generate the field in-place. This results in
MIDR_FUJITSU_ERRATUM_010001 being all-ones, and we only match A64FX
v0r0.
This patch uses MIDR_CPU_VAR_REV() to generate an in-place mask for the
variant field, ensuring the we match both v0r0 and v1r0.
Fixes: 3e32131abc311a5c ("arm64: Add workaround for Fujitsu A64FX erratum 010001")
Reported-by: "Okamoto, Takayuki" <tokamoto@jp.fujitsu.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[catalin.marinas@arm.com: fixed the patch author]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
1 parent 6a019a9
| File | Mode | Size |
|---|---|---|
| Kconfig | -rw-r--r-- | 623 bytes |
| Makefile | -rw-r--r-- | 316 bytes |
| csio_attr.c | -rw-r--r-- | 20.8 KB |
| csio_defs.h | -rw-r--r-- | 3.3 KB |
| csio_hw.c | -rw-r--r-- | 112.2 KB |
| csio_hw.h | -rw-r--r-- | 20.3 KB |
| csio_hw_chip.h | -rw-r--r-- | 4.2 KB |
| csio_hw_t5.c | -rw-r--r-- | 12.9 KB |
| csio_init.c | -rw-r--r-- | 28.7 KB |
| csio_init.h | -rw-r--r-- | 4.3 KB |
| csio_isr.c | -rw-r--r-- | 14.4 KB |
| csio_lnode.c | -rw-r--r-- | 53.9 KB |
| csio_lnode.h | -rw-r--r-- | 8.0 KB |
| csio_mb.c | -rw-r--r-- | 47.5 KB |
| csio_mb.h | -rw-r--r-- | 9.3 KB |
| csio_rnode.c | -rw-r--r-- | 22.6 KB |
| csio_rnode.h | -rw-r--r-- | 4.7 KB |
| csio_scsi.c | -rw-r--r-- | 67.0 KB |
| csio_scsi.h | -rw-r--r-- | 10.3 KB |
| csio_wr.c | -rw-r--r-- | 45.5 KB |
| csio_wr.h | -rw-r--r-- | 13.5 KB |
| t4fw_api_stor.h | -rw-r--r-- | 12.7 KB |
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