Revision 3dbcea54b3ff706c58f8e8d4470f5e5d3d24a6a0 authored by Mark Rutland on 15 March 2019, 12:22:36 UTC, committed by Catalin Marinas on 19 March 2019, 14:54:24 UTC
Fujitsu erratum 010001 applies to A64FX v0r0 and v1r0, and we try to
handle either by masking MIDR with MIDR_FUJITSU_ERRATUM_010001_MASK
before comparing it to MIDR_FUJITSU_ERRATUM_010001.
Unfortunately, MIDR_FUJITSU_ERRATUM_010001 is constructed incorrectly
using MIDR_VARIANT(), which is intended to extract the variant field
from MIDR_EL1, rather than generate the field in-place. This results in
MIDR_FUJITSU_ERRATUM_010001 being all-ones, and we only match A64FX
v0r0.
This patch uses MIDR_CPU_VAR_REV() to generate an in-place mask for the
variant field, ensuring the we match both v0r0 and v1r0.
Fixes: 3e32131abc311a5c ("arm64: Add workaround for Fujitsu A64FX erratum 010001")
Reported-by: "Okamoto, Takayuki" <tokamoto@jp.fujitsu.com>
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
[catalin.marinas@arm.com: fixed the patch author]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
1 parent 6a019a9
| File | Mode | Size |
|---|---|---|
| Kconfig | -rw-r--r-- | 479 bytes |
| Makefile | -rw-r--r-- | 191 bytes |
| cap.c | -rw-r--r-- | 2.9 KB |
| ctl.c | -rw-r--r-- | 24.3 KB |
| ctl.h | -rw-r--r-- | 4.6 KB |
| dma_port.c | -rw-r--r-- | 12.1 KB |
| dma_port.h | -rw-r--r-- | 937 bytes |
| domain.c | -rw-r--r-- | 18.8 KB |
| eeprom.c | -rw-r--r-- | 12.7 KB |
| icm.c | -rw-r--r-- | 49.9 KB |
| nhi.c | -rw-r--r-- | 29.9 KB |
| nhi.h | -rw-r--r-- | 1.8 KB |
| nhi_regs.h | -rw-r--r-- | 3.5 KB |
| path.c | -rw-r--r-- | 6.7 KB |
| property.c | -rw-r--r-- | 16.6 KB |
| switch.c | -rw-r--r-- | 39.5 KB |
| tb.c | -rw-r--r-- | 11.0 KB |
| tb.h | -rw-r--r-- | 15.5 KB |
| tb_msgs.h | -rw-r--r-- | 10.4 KB |
| tb_regs.h | -rw-r--r-- | 5.8 KB |
| tunnel_pci.c | -rw-r--r-- | 6.3 KB |
| tunnel_pci.h | -rw-r--r-- | 764 bytes |
| xdomain.c | -rw-r--r-- | 39.9 KB |
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