Revision 4272f98a1ae81709fc5c804c33c044064e419cd9 authored by Javi Merino on 16 November 2011, 11:36:39 UTC, committed by Russell King on 15 February 2012, 21:10:49 UTC
dst_cache_ctrl affects bits 3, 1 and 0 of AWCACHE but it is a 3-bit
field in the Channel Control Register (see Table 3-21 of the DMA-330
Technical Reference Manual) and should be programmed as such.

Reference: <1320244259-10496-3-git-send-email-javi.merino@arm.com>

Signed-off-by: Javi Merino <javi.merino@arm.com>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1 parent 8e43a90
History
File Mode Size
BUGS -rw-r--r-- 235 bytes
Kbuild -rw-r--r-- 527 bytes
Kconfig -rw-r--r-- 323 bytes
Kconfig.ore -rw-r--r-- 461 bytes
common.h -rw-r--r-- 8.6 KB
dir.c -rw-r--r-- 16.8 KB
exofs.h -rw-r--r-- 7.5 KB
file.c -rw-r--r-- 2.5 KB
inode.c -rw-r--r-- 36.4 KB
namei.c -rw-r--r-- 7.4 KB
ore.c -rw-r--r-- 29.0 KB
ore_raid.c -rw-r--r-- 19.0 KB
ore_raid.h -rw-r--r-- 2.7 KB
super.c -rw-r--r-- 26.1 KB
symlink.c -rw-r--r-- 1.8 KB

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