Revision 490d332ea42780577f679f5d13598b195bff360c authored by Marc Zyngier on 09 February 2020, 22:48:50 UTC, committed by Linus Torvalds on 09 February 2020, 23:47:37 UTC
In order to allow the GICv4 code to link properly on 32bit ARM, make sure we don't use 64bit divisions when it isn't strictly necessary. Fixes: 4e6437f12d6e ("irqchip/gic-v4.1: Ensure L2 vPE table is allocated at RD level") Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Zenghui Yu <yuzenghui@huawei.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
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File | Mode | Size |
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Kconfig | -rw-r--r-- | 3.2 KB |
Makefile | -rw-r--r-- | 701 bytes |
README | -rw-r--r-- | 7.9 KB |
acl.h | -rw-r--r-- | 1.8 KB |
bitmap.c | -rw-r--r-- | 39.6 KB |
dir.c | -rw-r--r-- | 9.0 KB |
do_balan.c | -rw-r--r-- | 54.0 KB |
file.c | -rw-r--r-- | 7.4 KB |
fix_node.c | -rw-r--r-- | 77.3 KB |
hashes.c | -rw-r--r-- | 3.5 KB |
ibalance.c | -rw-r--r-- | 34.3 KB |
inode.c | -rw-r--r-- | 92.4 KB |
ioctl.c | -rw-r--r-- | 5.3 KB |
item_ops.c | -rw-r--r-- | 18.1 KB |
journal.c | -rw-r--r-- | 120.1 KB |
lbalance.c | -rw-r--r-- | 41.2 KB |
lock.c | -rw-r--r-- | 2.6 KB |
namei.c | -rw-r--r-- | 43.9 KB |
objectid.c | -rw-r--r-- | 6.8 KB |
prints.c | -rw-r--r-- | 21.4 KB |
procfs.c | -rw-r--r-- | 13.2 KB |
reiserfs.h | -rw-r--r-- | 116.7 KB |
resize.c | -rw-r--r-- | 6.3 KB |
stree.c | -rw-r--r-- | 63.7 KB |
super.c | -rw-r--r-- | 70.0 KB |
tail_conversion.c | -rw-r--r-- | 9.2 KB |
xattr.c | -rw-r--r-- | 25.1 KB |
xattr.h | -rw-r--r-- | 3.7 KB |
xattr_acl.c | -rw-r--r-- | 9.6 KB |
xattr_security.c | -rw-r--r-- | 2.7 KB |
xattr_trusted.c | -rw-r--r-- | 1.2 KB |
xattr_user.c | -rw-r--r-- | 1.1 KB |
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