Revision 497d2214e5ba58ef55025b9951e7f9cccab760e4 authored by Mike Turquette on 06 January 2014, 05:36:43 UTC, committed by Mike Turquette on 06 January 2014, 05:36:43 UTC
Samsung Clock fixes for 3.13-rc7

* Several patches fixing up incorrectly defined register addresses and
  bitfield offsets that could lead to undefined operation when accessing
  respective registers or bitfields.

 1) clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks

 2a) clk: samsung: exynos5250: Fix ACP gate register offset
 2b) clk: samsung: exynos5250: Add MDMA0 clocks
 2c) ARM: dts: exynos5250: Fix MDMA0 clock number

 3) clk: samsung: exynos4: Correct SRC_MFC register

   All three issues have been present since Exynos5250 and Exynos4 clock
   drivers were added by commits 6e3ad26816b72 ("clk: exynos5250:
   register clocks using common clock framework") and e062b571777f5
   ("clk: exynos4: register clocks using common clock framework")
   respectively.

* Patch to fix automatic disabling of Exynos5250 sysreg clock that could
  cause undefined operation of several peripherals, such as USB, I2C,
  MIPI or display block.

 4) clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg
    clock

   Present since Exynos5250 clock drivers was added by commits
   6e3ad26816b72 ("clk: exynos5250: register clocks using common clock
   framework").

* Patch fixing compilation warning in clk-exynos-audss driver when
  CONFIG_PM_SLEEP is disabled.

 5) clk: exynos: File scope reg_save array should depend on PM_SLEEP

   Present since the driver was added by commit 1241ef94ccc3 ("clk:
   samsung: register audio subsystem clocks using common clock
   framework").
2 parent s d6e0a2d + 3fd68c9
Raw File
timeconst.bc
scale=0

define gcd(a,b) {
	auto t;
	while (b) {
		t = b;
		b = a % b;
		a = t;
	}
	return a;
}

/* Division by reciprocal multiplication. */
define fmul(b,n,d) {
       return (2^b*n+d-1)/d;
}

/* Adjustment factor when a ceiling value is used.  Use as:
   (imul * n) + (fmulxx * n + fadjxx) >> xx) */
define fadj(b,n,d) {
	auto v;
	d = d/gcd(n,d);
	v = 2^b*(d-1)/d;
	return v;
}

/* Compute the appropriate mul/adj values as well as a shift count,
   which brings the mul value into the range 2^b-1 <= x < 2^b.  Such
   a shift value will be correct in the signed integer range and off
   by at most one in the upper half of the unsigned range. */
define fmuls(b,n,d) {
	auto s, m;
	for (s = 0; 1; s++) {
		m = fmul(s,n,d);
		if (m >= 2^(b-1))
			return s;
	}
	return 0;
}

define timeconst(hz) {
	print "/* Automatically generated by kernel/timeconst.bc */\n"
	print "/* Time conversion constants for HZ == ", hz, " */\n"
	print "\n"

	print "#ifndef KERNEL_TIMECONST_H\n"
	print "#define KERNEL_TIMECONST_H\n\n"

	print "#include <linux/param.h>\n"
	print "#include <linux/types.h>\n\n"

	print "#if HZ != ", hz, "\n"
	print "#error \qkernel/timeconst.h has the wrong HZ value!\q\n"
	print "#endif\n\n"

	if (hz < 2) {
		print "#error Totally bogus HZ value!\n"
	} else {
		s=fmuls(32,1000,hz)
		obase=16
		print "#define HZ_TO_MSEC_MUL32\tU64_C(0x", fmul(s,1000,hz), ")\n"
		print "#define HZ_TO_MSEC_ADJ32\tU64_C(0x", fadj(s,1000,hz), ")\n"
		obase=10
		print "#define HZ_TO_MSEC_SHR32\t", s, "\n"

		s=fmuls(32,hz,1000)
		obase=16
		print "#define MSEC_TO_HZ_MUL32\tU64_C(0x", fmul(s,hz,1000), ")\n"
		print "#define MSEC_TO_HZ_ADJ32\tU64_C(0x", fadj(s,hz,1000), ")\n"
		obase=10
		print "#define MSEC_TO_HZ_SHR32\t", s, "\n"

		obase=10
		cd=gcd(hz,1000)
		print "#define HZ_TO_MSEC_NUM\t\t", 1000/cd, "\n"
		print "#define HZ_TO_MSEC_DEN\t\t", hz/cd, "\n"
		print "#define MSEC_TO_HZ_NUM\t\t", hz/cd, "\n"
		print "#define MSEC_TO_HZ_DEN\t\t", 1000/cd, "\n"
		print "\n"

		s=fmuls(32,1000000,hz)
		obase=16
		print "#define HZ_TO_USEC_MUL32\tU64_C(0x", fmul(s,1000000,hz), ")\n"
		print "#define HZ_TO_USEC_ADJ32\tU64_C(0x", fadj(s,1000000,hz), ")\n"
		obase=10
		print "#define HZ_TO_USEC_SHR32\t", s, "\n"

		s=fmuls(32,hz,1000000)
		obase=16
		print "#define USEC_TO_HZ_MUL32\tU64_C(0x", fmul(s,hz,1000000), ")\n"
		print "#define USEC_TO_HZ_ADJ32\tU64_C(0x", fadj(s,hz,1000000), ")\n"
		obase=10
		print "#define USEC_TO_HZ_SHR32\t", s, "\n"

		obase=10
		cd=gcd(hz,1000000)
		print "#define HZ_TO_USEC_NUM\t\t", 1000000/cd, "\n"
		print "#define HZ_TO_USEC_DEN\t\t", hz/cd, "\n"
		print "#define USEC_TO_HZ_NUM\t\t", hz/cd, "\n"
		print "#define USEC_TO_HZ_DEN\t\t", 1000000/cd, "\n"
		print "\n"

		print "#endif /* KERNEL_TIMECONST_H */\n"
	}
	halt
}

timeconst(hz)
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