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Revision 5846a73f26a1efa45e2c2edd36aa2ed0a6ad380a authored by Navare, Manasi D on 17 July 2017, 22:05:22 UTC, committed by Daniel Vetter on 27 July 2017, 20:07:22 UTC 
drm/i915/cnl: Fix loadgen select programming on ddi vswing sequence
 
The condition for setting the Loadgen Select bit of
PORT_TX_DW4 register during DDI Vswing Sequence should be
Bit rate <=6 GHz whereas the existing code checks only
Bit Rate < 6GHz. This patch fixes this condition.
While at it also remove the redundant paranthesis.

Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1500329122-32662-1-git-send-email-manasi.d.navare@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit a8e45a1c42d11597e975f3e5f2fe182f90cdaa7f)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
1 parent 283d686
Raw File
Kconfig 
#
# Performance Monitor Drivers
#

menu "Performance monitor support"
	depends on PERF_EVENTS

config ARM_PMU
	depends on ARM || ARM64
	bool "ARM PMU framework"
	default y
	help
	  Say y if you want to use CPU performance monitors on ARM-based
	  systems.

config ARM_PMU_ACPI
	depends on ARM_PMU && ACPI
	def_bool y

config QCOM_L2_PMU
	bool "Qualcomm Technologies L2-cache PMU"
	depends on ARCH_QCOM && ARM64 && ACPI
	  help
	  Provides support for the L2 cache performance monitor unit (PMU)
	  in Qualcomm Technologies processors.
	  Adds the L2 cache PMU into the perf events subsystem for
	  monitoring L2 cache events.

config QCOM_L3_PMU
	bool "Qualcomm Technologies L3-cache PMU"
	depends on ARCH_QCOM && ARM64 && ACPI
	select QCOM_IRQ_COMBINER
	help
	   Provides support for the L3 cache performance monitor unit (PMU)
	   in Qualcomm Technologies processors.
	   Adds the L3 cache PMU into the perf events subsystem for
	   monitoring L3 cache events.

config XGENE_PMU
        depends on ARCH_XGENE
        bool "APM X-Gene SoC PMU"
        default n
        help
          Say y if you want to use APM X-Gene SoC performance monitors.

endmenu
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