Revision 5846a73f26a1efa45e2c2edd36aa2ed0a6ad380a authored by Navare, Manasi D on 17 July 2017, 22:05:22 UTC, committed by Daniel Vetter on 27 July 2017, 20:07:22 UTC
The condition for setting the Loadgen Select bit of
PORT_TX_DW4 register during DDI Vswing Sequence should be
Bit rate <=6 GHz whereas the existing code checks only
Bit Rate < 6GHz. This patch fixes this condition.
While at it also remove the redundant paranthesis.
Fixes: cf54ca8bc567 ("drm/i915/cnl: Implement voltage swing sequence.")
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1500329122-32662-1-git-send-email-manasi.d.navare@intel.com
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
(cherry picked from commit a8e45a1c42d11597e975f3e5f2fe182f90cdaa7f)
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
1 parent 283d686
| File | Mode | Size |
|---|---|---|
| Kconfig | -rw-r--r-- | 479 bytes |
| Makefile | -rw-r--r-- | 170 bytes |
| cap.c | -rw-r--r-- | 2.9 KB |
| ctl.c | -rw-r--r-- | 24.4 KB |
| ctl.h | -rw-r--r-- | 4.5 KB |
| dma_port.c | -rw-r--r-- | 12.4 KB |
| dma_port.h | -rw-r--r-- | 1.1 KB |
| domain.c | -rw-r--r-- | 10.4 KB |
| eeprom.c | -rw-r--r-- | 12.4 KB |
| icm.c | -rw-r--r-- | 26.6 KB |
| nhi.c | -rw-r--r-- | 23.2 KB |
| nhi.h | -rw-r--r-- | 5.6 KB |
| nhi_regs.h | -rw-r--r-- | 3.5 KB |
| path.c | -rw-r--r-- | 6.7 KB |
| switch.c | -rw-r--r-- | 35.2 KB |
| tb.c | -rw-r--r-- | 10.9 KB |
| tb.h | -rw-r--r-- | 14.5 KB |
| tb_msgs.h | -rw-r--r-- | 5.4 KB |
| tb_regs.h | -rw-r--r-- | 5.8 KB |
| tunnel_pci.c | -rw-r--r-- | 6.3 KB |
| tunnel_pci.h | -rw-r--r-- | 725 bytes |
Computing file changes ...
