Revision 584ee3dcb1d6232857c1e38bb28d9f6bf0ec89f5 authored by Alexandra Yates on 18 November 2015, 22:58:40 UTC, committed by Rafael J. Wysocki on 25 November 2015, 22:37:44 UTC
If hardware-driven P-state selection (HWP) is enabled, the "performance" mode of intel_pstate should only allow the processor to use the highest-performance P-state available. That is not the case currently, so make it actually happen. Acked-by: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Alexandra Yates <alexandra.yates@linux.intel.com> [ rjw: Subject and changelog ] Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
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| File | Mode | Size |
|---|---|---|
| Kconfig | -rw-r--r-- | 4.0 KB |
| Makefile | -rw-r--r-- | 896 bytes |
| b43_pci_bridge.c | -rw-r--r-- | 1.8 KB |
| bridge_pcmcia_80211.c | -rw-r--r-- | 2.7 KB |
| driver_chipcommon.c | -rw-r--r-- | 17.8 KB |
| driver_chipcommon_pmu.c | -rw-r--r-- | 21.9 KB |
| driver_chipcommon_sflash.c | -rw-r--r-- | 4.1 KB |
| driver_extif.c | -rw-r--r-- | 5.0 KB |
| driver_gige.c | -rw-r--r-- | 7.3 KB |
| driver_gpio.c | -rw-r--r-- | 11.8 KB |
| driver_mipscore.c | -rw-r--r-- | 8.7 KB |
| driver_pcicore.c | -rw-r--r-- | 18.7 KB |
| embedded.c | -rw-r--r-- | 6.2 KB |
| host_soc.c | -rw-r--r-- | 3.5 KB |
| main.c | -rw-r--r-- | 30.5 KB |
| pci.c | -rw-r--r-- | 37.0 KB |
| pcihost_wrapper.c | -rw-r--r-- | 2.9 KB |
| pcmcia.c | -rw-r--r-- | 19.3 KB |
| scan.c | -rw-r--r-- | 10.2 KB |
| sdio.c | -rw-r--r-- | 15.6 KB |
| sprom.c | -rw-r--r-- | 5.2 KB |
| ssb_private.h | -rw-r--r-- | 8.0 KB |
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