https://github.com/torvalds/linux
Revision 589b64a7e39720b1784a1a26569c57cb977936ef authored by changzhu on 10 October 2019, 03:02:33 UTC, committed by Alex Deucher on 07 November 2019, 03:06:23 UTC
The GRBM register interface is now capable of bursting 1 cycle per register wr->wr, wr->rd much faster than previous muticycle per transaction done interface. This has caused a problem where status registers requiring HW to update have a 1 cycle delay, due to the register update having to go through GRBM. For cp ucode, it has realized dummy read in cp firmware.It covers the use of WAIT_REG_MEM operation 1 case only.So it needs to call gfx_v10_0_wait_reg_mem in gfx10. Besides it also needs to add warning to update firmware in case firmware is too old to have function to realize dummy read in cp firmware. For sdma ucode, it hasn't realized dummy read in sdma firmware. sdma is moved to gfxhub in gfx10. So it needs to add dummy read in driver between amdgpu_ring_emit_wreg and amdgpu_ring_emit_reg_wait for sdma_v5_0. Signed-off-by: changzhu <Changfeng.Zhu@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 6a299d7
Tip revision: 589b64a7e39720b1784a1a26569c57cb977936ef authored by changzhu on 10 October 2019, 03:02:33 UTC
drm/amdgpu: add dummy read by engines for some GCVM status registers in gfx10
drm/amdgpu: add dummy read by engines for some GCVM status registers in gfx10
Tip revision: 589b64a
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