Revision 5a2913aadabc4711e98fb48d56e5c5f5728bbc33 authored by Le Ma on 07 November 2023, 10:10:29 UTC, committed by Alex Deucher on 09 November 2023, 22:00:55 UTC
The DS clock may exceed the limit as sclk dfll divider is 16
to target freq.

Signed-off-by: Le Ma <le.ma@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Reviewed-by: Yang Wang <kevinyang.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
1 parent 4eaa007
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