Revision 5b2e31201c268c2331a209af799d667619216d40 authored by Chris Wilson on 07 December 2018, 13:40:37 UTC, committed by Joonas Lahtinen on 12 December 2018, 10:27:44 UTC
Adding an extra MI_STORE_DWORD_IMM to the gpu relocation path for gen3 was good, but still not good enough. To survive 24+ hours under test we needed to perform not one, not two but three extra store-dw. Doing so for each GPU relocation was a little unsightly and since we need to worry about userspace hitting the same issues, we should apply the dummy store-dw into the EMIT_FLUSH. Fixes: 7dd4f6729f92 ("drm/i915: Async GPU relocation processing") References: 7fa28e146994 ("drm/i915: Write GPU relocs harder with gen3") Testcase: igt/gem_tiled_fence_blits # blb/pnv Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Reviewed-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20181207134037.11848-1-chris@chris-wilson.co.uk (cherry picked from commit a889580c087a9cf91fddb3832ece284174214183) Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
1 parent fe78742
File | Mode | Size |
---|---|---|
BSD-2-Clause | -rw-r--r-- | 1.6 KB |
BSD-3-Clause | -rw-r--r-- | 1.8 KB |
BSD-3-Clause-Clear | -rw-r--r-- | 2.0 KB |
GPL-2.0 | -rw-r--r-- | 18.3 KB |
LGPL-2.0 | -rw-r--r-- | 25.6 KB |
LGPL-2.1 | -rw-r--r-- | 26.8 KB |
MIT | -rw-r--r-- | 1.3 KB |
Computing file changes ...