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Revision 66218da212bf141532d678a699f5789c78145ab1 authored by Atsushi Nemoto on 24 January 2007, 06:43:34 UTC, committed by Ralf Baechle on 24 January 2007, 19:23:22 UTC 
[MIPS] Fix wrong checksum calculation on 64-bit MIPS
 
The commit 8e3d8433d8c22ca6c42cba4a67d300c39aae7822 ([NET]: MIPS
checksum annotations and cleanups) broke 64-bit MIPS.

The problem is the commit replaces some unsigned long with __be32.  On
64bit MIPS, a __be32 (i.e. unsigned int) value is represented as a
sign-extented 32-bit value in a 64-bit argument register.  So the
address 192.168.0.1 (0xc0a80001) is passed as 0xffffffffc0a80001 to
csum_tcpudp_nofold() but the asm code in the function expects
0x00000000c0a80001, therefore it returns a wrong checksum.  Explicit
cast to unsigned long is needed to drop high 32bit.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1 parent 9cfdf6f
Raw File
irc-regs.h 
/* irc-regs.h: on-chip interrupt controller registers
 *
 * Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
 * Written by David Howells (dhowells@redhat.com)
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version
 * 2 of the License, or (at your option) any later version.
 */

#ifndef _ASM_IRC_REGS
#define _ASM_IRC_REGS

#define __reg(ADDR) (*(volatile unsigned long *)(ADDR))

#define __get_TM0()	({ __reg(0xfeff9800); })
#define __get_TM1()	({ __reg(0xfeff9808); })
#define __set_TM1(V)	do { __reg(0xfeff9808) = (V); mb(); } while(0)

#define __set_TM1x(XI,V)			\
do {						\
	int shift = (XI) * 2 + 16;		\
	unsigned long tm1 = __reg(0xfeff9808);	\
	tm1 &= ~(0x3 << shift);			\
	tm1 |= (V) << shift;			\
	__reg(0xfeff9808) = tm1;		\
	mb();					\
} while(0)

#define __get_RS(C)	({ (__reg(0xfeff9810) >> ((C)+16)) & 1; })

#define __clr_RC(C)	do { __reg(0xfeff9818) = 1 << ((C)+16); mb(); } while(0)

#define __get_MASK(C)	({ (__reg(0xfeff9820) >> ((C)+16)) & 1; })
#define __set_MASK(C)	do { __reg(0xfeff9820) |=  1 << ((C)+16); mb(); } while(0)
#define __clr_MASK(C)	do { __reg(0xfeff9820) &=  ~(1 << ((C)+16)); mb(); } while(0)

#define __get_MASK_all() __get_MASK(0)
#define __set_MASK_all() __set_MASK(0)
#define __clr_MASK_all() __clr_MASK(0)

#define __get_IRL()	({ (__reg(0xfeff9828) >> 16) & 0xf; })
#define __clr_IRL()	do { __reg(0xfeff9828) = 0x100000; mb(); } while(0)

#define __get_IRR(N)	({ __reg(0xfeff9840 + (N) * 8); })
#define __set_IRR(N,V)	do { __reg(0xfeff9840 + (N) * 8) = (V); } while(0)

#define __get_IITMR(N)	({ __reg(0xfeff9880 + (N) * 8); })
#define __set_IITMR(N,V) do { __reg(0xfeff9880 + (N) * 8) = (V); } while(0)


#endif /* _ASM_IRC_REGS */
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