Revision 66218da212bf141532d678a699f5789c78145ab1 authored by Atsushi Nemoto on 24 January 2007, 06:43:34 UTC, committed by Ralf Baechle on 24 January 2007, 19:23:22 UTC
The commit 8e3d8433d8c22ca6c42cba4a67d300c39aae7822 ([NET]: MIPS checksum annotations and cleanups) broke 64-bit MIPS. The problem is the commit replaces some unsigned long with __be32. On 64bit MIPS, a __be32 (i.e. unsigned int) value is represented as a sign-extented 32-bit value in a 64-bit argument register. So the address 192.168.0.1 (0xc0a80001) is passed as 0xffffffffc0a80001 to csum_tcpudp_nofold() but the asm code in the function expects 0x00000000c0a80001, therefore it returns a wrong checksum. Explicit cast to unsigned long is needed to drop high 32bit. Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
1 parent 9cfdf6f
mb86943a.h
/* mb86943a.h: MB86943 SPARClite <-> PCI bridge registers
*
* Copyright (C) 2003 Red Hat, Inc. All Rights Reserved.
* Written by David Howells (dhowells@redhat.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#ifndef _ASM_MB86943A_H
#define _ASM_MB86943A_H
#include <asm/mb-regs.h>
#define __reg_MB86943_sl_ctl *(volatile uint32_t *) (__region_CS1 + 0x00)
#define MB86943_SL_CTL_BUS_WIDTH_64 0x00000001
#define MB86943_SL_CTL_AS_HOST 0x00000002
#define MB86943_SL_CTL_DRCT_MASTER_SWAP 0x00000004
#define MB86943_SL_CTL_DRCT_SLAVE_SWAP 0x00000008
#define MB86943_SL_CTL_PCI_CONFIG_SWAP 0x00000010
#define MB86943_SL_CTL_ECS0_ENABLE 0x00000020
#define MB86943_SL_CTL_ECS1_ENABLE 0x00000040
#define MB86943_SL_CTL_ECS2_ENABLE 0x00000080
#define __reg_MB86943_ecs_ctl(N) *(volatile uint32_t *) (__region_CS1 + 0x08 + (0x08*(N)))
#define __reg_MB86943_ecs_range(N) *(volatile uint32_t *) (__region_CS1 + 0x20 + (0x10*(N)))
#define __reg_MB86943_ecs_base(N) *(volatile uint32_t *) (__region_CS1 + 0x28 + (0x10*(N)))
#define __reg_MB86943_sl_pci_io_range *(volatile uint32_t *) (__region_CS1 + 0x50)
#define __reg_MB86943_sl_pci_io_base *(volatile uint32_t *) (__region_CS1 + 0x58)
#define __reg_MB86943_sl_pci_mem_range *(volatile uint32_t *) (__region_CS1 + 0x60)
#define __reg_MB86943_sl_pci_mem_base *(volatile uint32_t *) (__region_CS1 + 0x68)
#define __reg_MB86943_pci_sl_io_base *(volatile uint32_t *) (__region_CS1 + 0x70)
#define __reg_MB86943_pci_sl_mem_base *(volatile uint32_t *) (__region_CS1 + 0x78)
#endif /* _ASM_MB86943A_H */
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