Revision 6639484ddaf6707b41082c9fa9ca9af342df6402 authored by Libin Yang on 29 January 2016, 12:39:09 UTC, committed by Takashi Iwai on 29 January 2016, 13:00:41 UTC
On Broxton, to make sure the reset controller works properly, MISCBDCGE bit (bit 6) in CGCTL (0x48) of PCI configuration space need be cleared before reset and set back to 1 after reset. Otherwise, it may prevent the CORB/RIRB logic from being reset. Signed-off-by: Libin Yang <libin.yang@linux.intel.com> Cc: <stable@vger.kernel.org> # v4.4+ Signed-off-by: Takashi Iwai <tiwai@suse.de>
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| File | Mode | Size |
|---|---|---|
| Documentation | ||
| arch | ||
| block | ||
| certs | ||
| crypto | ||
| drivers | ||
| firmware | ||
| fs | ||
| include | ||
| init | ||
| ipc | ||
| kernel | ||
| lib | ||
| mm | ||
| net | ||
| samples | ||
| scripts | ||
| security | ||
| sound | ||
| tools | ||
| usr | ||
| virt | ||
| .get_maintainer.ignore | -rw-r--r-- | 31 bytes |
| .gitignore | -rw-r--r-- | 1.2 KB |
| .mailmap | -rw-r--r-- | 5.4 KB |
| COPYING | -rw-r--r-- | 18.3 KB |
| CREDITS | -rw-r--r-- | 95.4 KB |
| Kbuild | -rw-r--r-- | 2.6 KB |
| Kconfig | -rw-r--r-- | 252 bytes |
| MAINTAINERS | -rw-r--r-- | 337.2 KB |
| Makefile | -rw-r--r-- | 53.7 KB |
| README | -rw-r--r-- | 18.2 KB |
| REPORTING-BUGS | -rw-r--r-- | 7.3 KB |
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