https://github.com/torvalds/linux
Revision 691557941af4c12bd307ad81a4d9fa9c7743ac28 authored by Jon Medhurst on 07 June 2013, 09:35:35 UTC, committed by Russell King on 17 June 2013, 09:30:49 UTC
On Cortex-A9 before version r1p0, the LoUIS bit field of the CLIDR
register returns zero when it should return one. This leads to cache
maintenance operations which rely on this value to not function as
intended, causing data corruption.

The workaround for this errata is to detect affected CPUs and correct
the LoUIS value read.

Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Cc: stable@vger.kernel.org
Signed-off-by: Jon Medhurst <tixy@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1 parent 509eb76
History
Tip revision: 691557941af4c12bd307ad81a4d9fa9c7743ac28 authored by Jon Medhurst on 07 June 2013, 09:35:35 UTC
ARM: 7752/1: errata: LoUIS bit field in CLIDR register is incorrect
Tip revision: 6915579
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