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swh:1:snp:77163734605b0ec556b01d897b7bb4a7e30d46b6
Revision 6a0e243069b09a323255f6e847c87d531961cd96 authored by Catalin Marinas on 07 March 2006, 14:42:27 UTC, committed by Russell King on 07 March 2006, 14:42:27 UTC 
[ARM] 3352/1: DSB required for the completion of a TLB maintenance operation
 
Patch from Catalin Marinas

Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that
the completion of a TLB maintenance operation is only guaranteed by
the execution of a DSB (Data Syncronization Barrier, formerly Data
Write Barrier or Drain Write Buffer).

Note that a DSB is only needed in the flush_tlb_kernel_* functions
since the completion is guaranteed by a mode change (i.e. switching
back to user mode) for the flush_tlb_user_* functions.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
1 parent d11d9b2
History
Tip revision: a4412fdd49dc011bcc2c0d81ac4cab7457092650 authored by Steven Rostedt (Google) on 21 November 2022, 15:44:03 UTC
error-injection: Add prompt for function error injection
Tip revision: a4412fd
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